公开(公告)号：US20230232628A1

公开(公告)日：2023-07-20

申请号：US17963320

申请日：2022-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Subin SHIN ,  Sangwon KIM ,  Jeeyong KIM ,  Hyeonjoo SONG ,  Habin LIM

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/5283

Abstract: A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

公开(公告)号：US20220199767A1

公开(公告)日：2022-06-23

申请号：US17468814

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi LEE ,  Seongjae GO ,  Hyeonjoo SONG ,  Sunjoong PARK ,  Hanyong PARK

IPC: H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/065

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

公开(公告)号：US20250072064A1

公开(公告)日：2025-02-27

申请号：US18945603

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyemi LEE ,  Seongjae GO ,  Hyeonjoo SONG ,  Sunjoong PARK ,  Hanyong PARK

IPC: H01L29/06 ,  G11C5/06 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

公开(公告)号：US20230058328A1

公开(公告)日：2023-02-23

申请号：US17739583

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin LEE ,  Byoung-Taek KIM ,  Hyeonjoo SONG

IPC: H01L23/535 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.

公开(公告)号：US20220310801A1

公开(公告)日：2022-09-29

申请号：US17530651

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjoo SONG ,  Byoungtaek KIM ,  Haemin LEE

IPC: H01L29/40 ,  H01L27/11582 ,  H01L23/48

Abstract: A semiconductor device includes a substrate, gate electrodes stacked in a first direction, channel structures penetrating through the gate electrodes, a horizontal conductive layer below the gate electrodes on the substrate, separation regions penetrating through the gate electrodes and the horizontal conductive layer, and extending in the first and second directions, a cell region insulating layer covering the gate electrodes, and an upper support layer on the separation regions and the cell region insulating layer and having openings to overlap the separation regions. Each of the separation regions includes a contact conductive layer and a first separation insulating layer in a trench, and has first regions below the openings and second regions alternating with the first regions. The contact conductive layer is in contact with the substrate in the first regions, and is spaced apart from the substrate by the first separation insulating layer in the second regions.