公开(公告)号：US20130242635A1

公开(公告)日：2013-09-19

申请号：US13795567

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min YU ,  Ho-Young SONG ,  Sung-Min SEO ,  Sang-Joon HWANG

IPC: G11C17/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C17/18

Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Abstract translation: 半导体存储器件包括：存储单元阵列，被配置为存储包括验证码的数据; 感测单元，被配置为感测存储的包括验证码的数据; 以及验证单元，被配置为基于感测条件来确定所述感测单元是否能够感测所存储的数据，其中所述验证单元被配置为基于所述感测条件来确定所述感测单元是否能够感测所存储的数据，以及 由感测单元感测的验证码的值。

公开(公告)号：US20170011792A1

公开(公告)日：2017-01-12

申请号：US15134637

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min OH ,  Ho-Young SONG ,  Do-Yeon KIM

IPC: G11C11/406 ,  G11C7/10

Abstract: Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.

Abstract translation: 提供包括在内存设备和包括嵌入式刷新控制器的存储设备中的嵌入式刷新控制器。 嵌入式刷新控制器可以包括刷新计数器和地址生成器。 刷新计数器可以响应于计数器刷新信号而生成计数器刷新地址信号，使得计数器刷新地址信号可以表示顺序变化的地址。 地址生成器可以存储关于密集访问的音锤地址的信息，并且可以响应于音锤刷新信号而产生音锤刷新地址信号，使得音锤刷新地址信号可以表示与物理上相邻的行的地址 一排锤子地址。 可以通过检测集中访问的锤地址并且基于检测到的锤地址有效地执行刷新操作，可以减少存储器件的损耗并且可以提高存储器件的性能。

公开(公告)号：US20190354292A1

公开(公告)日：2019-11-21

申请号：US16524749

申请日：2019-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

IPC: G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US20170186481A1

公开(公告)日：2017-06-29

申请号：US15262183

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min OH ,  Ho-Young SONG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C11/406

Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

公开(公告)号：US20180366615A1

公开(公告)日：2018-12-20

申请号：US15841937

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi-Goo Kang ,  Sun-Woo KIM ,  Jong-Sup SONG ,  Ho-Young SONG

IPC: H01L33/44 ,  H01L33/48 ,  H01L33/38 ,  H01L23/00

Abstract: A packaged light emitting device can include a mounting substrate including first and second electrode portions that are separated by a recess defined by a first side surface of the first electrode portion and a second side surface of the second electrode portion that is opposite the first side surface. An insulation support member can partially fill a lower portion of the recess to partially cover the first side surface and partially cover the second side surface. A light emitting device can be coupled to the first and second electrode portions of the mounting substrate and a sealing member can be on the mounting substrate covering the light emitting device.

公开(公告)号：US20170148501A1

公开(公告)日：2017-05-25

申请号：US15341245

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Ho-Young SONG

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40607 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.

公开(公告)号：US20160189800A1

公开(公告)日：2016-06-30

申请号：US14970983

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min RYU ,  Ho-Young SONG ,  Yun-Young LEE

IPC: G11C29/00 ,  G11C8/10 ,  G11C17/16

CPC classification number: G11C29/40 ,  G06F11/006 ,  G11C8/10 ,  G11C17/00 ,  G11C17/143 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/76

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件可以包括第一单元阵列，第一熔丝电路，第一备用单元阵列，第二备用单元阵列和冗余选择控制器。 第一熔丝电路可以被配置为存储对应于第一单元阵列中的一个或多个有缺陷的存储器单元的第一失败地址。 第一和第二备用单元阵列中的每一个可以包括分别替换第一单元阵列中的第一和第二有缺陷存储单元的多个备用存储单元。 为了替换第一和第二有缺陷的存储器单元，冗余选择控制器可以被配置为选择性地将第一熔丝电路分配给第一和第二备用单元阵列中的一个或两个。

公开(公告)号：US20140104921A1

公开(公告)日：2014-04-17

申请号：US14049399

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min YU ,  Sung-Min SEO ,  Ho-Young SONG ,  Gil-Su KIM ,  Jong-Min OH

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。