公开(公告)号：US20170192721A1

公开(公告)日：2017-07-06

申请号：US15462347

申请日：2017-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-ju CHUNG ,  Su-a KIM ,  Mu-jin SEO ,  Hak-soo YU ,  Jae-youn YOUN ,  Hyo-jin CHOI

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C11/409 ,  G11C29/52 ,  G11C29/783

Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

公开(公告)号：US20220292033A1

公开(公告)日：2022-09-15

申请号：US17591928

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-soo YU ,  Shinhaeng KANG ,  Yuhwan RO

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

公开(公告)号：US20170352434A1

公开(公告)日：2017-12-07

申请号：US15600715

申请日：2017-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min RYU ,  Hak-soo YU ,  Reum OH ,  Seong-young SEO ,  Soo-jung RHO

IPC: G11C29/12 ,  G11C5/00 ,  G11C29/26 ,  G11C29/54

CPC classification number: G11C29/12 ,  G11C5/005 ,  G11C5/04 ,  G11C29/14 ,  G11C29/26 ,  G11C29/46 ,  G11C29/54 ,  G11C2029/0409 ,  G11C2029/1208 ,  G11C2029/2602

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

公开(公告)号：US20240419612A1

公开(公告)日：2024-12-19

申请号：US18819544

申请日：2024-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-soo YU ,  Shinhaeng KANG ,  Yuhwan RO

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

公开(公告)号：US20240379150A1

公开(公告)日：2024-11-14

申请号：US18782884

申请日：2024-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar KASIBHATLA ,  Seong-il O ,  Hak-soo YU

IPC: G11C11/4091 ,  G06F15/78 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20230360693A1

公开(公告)日：2023-11-09

申请号：US18223078

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar KASIBHATLA ,  Seong-il O. ,  Hak-soo YU

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4087 ,  G06F15/7821 ,  G11C11/4096 ,  G11C7/1006 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.