公开(公告)号：US20170352434A1

公开(公告)日：2017-12-07

申请号：US15600715

申请日：2017-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min RYU ,  Hak-soo YU ,  Reum OH ,  Seong-young SEO ,  Soo-jung RHO

IPC: G11C29/12 ,  G11C5/00 ,  G11C29/26 ,  G11C29/54

CPC classification number: G11C29/12 ,  G11C5/005 ,  G11C5/04 ,  G11C29/14 ,  G11C29/26 ,  G11C29/46 ,  G11C29/54 ,  G11C2029/0409 ,  G11C2029/1208 ,  G11C2029/2602

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

公开(公告)号：US20170125119A1

公开(公告)日：2017-05-04

申请号：US15232586

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang-gyoon LOH ,  Je-min RYU ,  Hyun-ki KIM ,  Yoon-jae JEONG

IPC: G11C17/18 ,  G11C17/16 ,  G11C29/12

CPC classification number: G11C17/18 ,  G11C8/12 ,  G11C17/16 ,  G11C29/1201 ,  G11C29/88 ,  G11C2029/4402

Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.