公开(公告)号：US20130100755A1

公开(公告)日：2013-04-25

申请号：US13653799

申请日：2012-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-youn YOUN ,  Hyo-chang KIM ,  Sang-jae RHEE

IPC: G11C7/00

CPC classification number: G11C11/40622 ,  G11C11/40615

Abstract: A semiconductor memory device performing a comprehensive partial self refresh (CPSR) scheme, in which a CPSR operation of not performing a self refresh operation on the segments included in each bank is disclosed. The semiconductor memory device includes a mask information register configured to generate mask information by storing information indicating a bank and a segment on which the self refresh operation is not performed; and a mask operation circuit configured to not perform the self refresh operation on the segments of each of the banks in response to the mask information. The semiconductor memory device efficiently performs a refresh operation according to user convenience and supports lower power consumption.

Abstract translation: 一种执行全面部分自刷新（CPSR）方案的半导体存储器件，其中公开了对每个存储体中包括的片段不执行自刷新操作的CPSR操作。 半导体存储器件包括：掩模信息寄存器，被配置为通过存储指示不执行自刷新操作的段和段的信息来生成掩码信息; 以及掩模操作电路，被配置为响应于掩模信息而不对每个存储体的段执行自刷新操作。 半导体存储装置根据用户的便利有效地执行刷新操作，并支持较低的功耗。

公开(公告)号：US20170192721A1

公开(公告)日：2017-07-06

申请号：US15462347

申请日：2017-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-ju CHUNG ,  Su-a KIM ,  Mu-jin SEO ,  Hak-soo YU ,  Jae-youn YOUN ,  Hyo-jin CHOI

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C11/409 ,  G11C29/52 ,  G11C29/783

Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.