公开(公告)号：US20220384410A1

公开(公告)日：2022-12-01

申请号：US17883682

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNMOG PARK ,  DAEHYUN KIM ,  JINMIN KIM ,  HEI SEUNG KIM ,  HYUNSIK PARK ,  SANGKIL LEE

IPC: H01L25/18 ,  G11C14/00 ,  G11C16/04 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/48

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

公开(公告)号：US20220013525A1

公开(公告)日：2022-01-13

申请号：US17172124

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIN HEE CHO ,  HYUNMOG PARK ,  WOO BIN SONG ,  MINSU LEE ,  WONSOK LEE

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.

公开(公告)号：US20170207234A1

公开(公告)日：2017-07-20

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNMOG PARK ,  DAEWOONG KANG ,  CHADONG YEO ,  JAEHOON JANG ,  JOONGSHIK SHIN

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L27/11529 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/16 ,  H01L29/4966

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.