公开(公告)号：US20230267995A1

公开(公告)日：2023-08-24

申请号：US18161303

申请日：2023-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Dukhyun Choe ,  Jinseong Heo ,  Hyunjae Lee

IPC: G11C11/54 ,  H01L29/78 ,  H01L29/51 ,  H10B53/30 ,  H01L29/66 ,  H01L27/105 ,  H01L21/02 ,  G11C11/22

CPC classification number: G11C11/54 ,  H01L29/78391 ,  H01L29/516 ,  H10B53/30 ,  H01L29/6684 ,  H01L27/105 ,  H01L21/02175 ,  G11C11/2255 ,  G11C11/2257

Abstract: Provided are a ferroelectric field effect transistor, a neural network apparatus, and an electronic apparatus. The ferroelectric field effect transistor includes: a substrate; a source protruding from an upper surface of the substrate in a first direction; a drain protruding from the upper surface of the substrate in the first direction; a channel spaced apart from the upper surface of the substrate and extending between the source and the drain in a second direction different from the first direction; a ferroelectric film surrounding an outer circumferential surface of the channel; and a gate electrode surrounding the ferroelectric film, wherein the channel has curved cross-sections having a plurality of different radii of curvature.

公开(公告)号：US12132109B2

公开(公告)日：2024-10-29

申请号：US17677654

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul Bae ,  Seunggeol Nam ,  Jinseong Heo ,  Sanghyun Jo ,  Dukhyun Choe

IPC: H01L29/06 ,  H01L21/66 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L22/12 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3eV−1 or more and an interface defect density of 1010 cm−2eV−1 or more.

公开(公告)号：US11843037B2

公开(公告)日：2023-12-12

申请号：US17496300

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun Choe ,  Jinseong Heo ,  Yunseong Lee ,  Sanghyun Jo

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H10K10/46

CPC classification number: H01L29/408 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/6684 ,  H01L29/7833 ,  H01L29/78391 ,  H10K10/474 ,  H01L29/516

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a channel layer at least one of on or in the substrate, an insulation layer on the substrate, a ferroelectric layer on the insulation layer, a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity, and a gate on the ferroelectric layer.

公开(公告)号：US12266710B2

公开(公告)日：2025-04-01

申请号：US17518015

申请日：2021-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun Choe ,  Jinseong Heo ,  Taehwan Moon ,  Sanghyun Jo

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786

Abstract: Provided are a thin film structure, a semiconductor device including the thin film structure, and a semiconductor apparatus including the semiconductor device. The thin film structure includes a substrate, and a ferroelectric layer on the substrate. The ferroelectric layer includes a compound having fluorite structure, in which a crystal direction is aligned in a normal direction of a substrate, and having an orthorhombic phase and including fluorine. The ferroelectric layer may have ferroelectricity.

公开(公告)号：US12218217B2

公开(公告)日：2025-02-04

申请号：US17545442

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong Lee ,  Jinseong Heo ,  Taehwan Moon ,  Seunggeol Nam ,  Dukhyun Choe

IPC: H01L29/51 ,  H10B51/00 ,  H10B53/00

Abstract: A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an anti-ferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.

公开(公告)号：US12119060B2

公开(公告)日：2024-10-15

申请号：US17953491

申请日：2022-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Hagyoul Bae ,  Seunggeol Nam ,  Hyunjae Lee ,  Dukhyun Choe

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Provided is a content-addressable memory. The content-addressable memory may include a memory cell connected to a match line, a word line, and a search line, and the memory cell includes a first channel layer and a second channel layer doped with different dopants.