公开(公告)号：US20230119406A1

公开(公告)日：2023-04-20

申请号：US17842262

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pilsung CHOI ,  Donguk KWON ,  Sangsoo KIM ,  Wooram MYUNG ,  Jiwon SHIN ,  Sehun AHN

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, the semiconductor chip including a first surface facing the lower substrate and a second surface opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate including a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of the semiconductor chip and the connection structure; and adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with the second surface and the support members.

公开(公告)号：US20240049400A1

公开(公告)日：2024-02-08

申请号：US18127531

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngja KIM ,  Donguk KWON ,  Youngmin LEE ,  Byungkeun KANG ,  Gongmyeong KIM ,  Chaein MOON

IPC: H05K3/34 ,  H01L23/00

CPC classification number: H05K3/3494 ,  H01L24/13 ,  H05K3/3447 ,  H01L2224/81815

Abstract: A method of manufacturing an electronic device, includes: providing a substrate including a plurality of mounting regions on which electronic components are mounted respectively; forming a plurality of vapor passage holes that penetrate the substrate; disposing the electronic components on the substrate via bumps; heating a first heat transfer fluid to generate a second heat transfer fluid in a vapor state; supplying at least a portion of the second heat transfer fluid in the vapor state through the vapor passage holes of the substrate; and soldering the bumps using the at least the portion of the second heat transfer fluid in the vapor state.

公开(公告)号：US20250167015A1

公开(公告)日：2025-05-22

申请号：US18668361

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donguk KWON

IPC: H01L21/67 ,  H01L21/60 ,  H01L21/603 ,  H01L21/683 ,  H01L23/00

Abstract: The inventive concept relates to an apparatus for manufacturing a semiconductor package and a method of manufacturing a semiconductor package. According to embodiments, the method of manufacturing a semiconductor package may include preparing a substrate including upper conductive pads on an upper surface of the substrate, preparing a first semiconductor chip including first solder balls, wherein a first dielectric layer covering sidewalls of the first solder balls is on a lower surface of the first semiconductor chip, disposing the first semiconductor chip on the substrate such that the first solder balls are on the upper conductive pads, and bonding the first solder balls to the upper conductive pads by applying an alternating current electric field to the first dielectric layer.

公开(公告)号：US20230091131A1

公开(公告)日：2023-03-23

申请号：US17739329

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Jiwon SHIN ,  Donguk KWON ,  Wooram MYUNG ,  Kwangbok WOO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

公开(公告)号：US20230132054A1

公开(公告)日：2023-04-27

申请号：US17848562

申请日：2022-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooram MYUNG ,  Donguk KWON ,  Jiwon SHIN ,  KyeongHwan JO ,  Pilsung CHOI

IPC: H01L23/00

Abstract: Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.

公开(公告)号：US20230099351A1

公开(公告)日：2023-03-30

申请号：US17844815

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk KWON ,  Wooram MYUNG ,  Jiwon SHIN ,  Pilsung CHOI

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

公开(公告)号：US20220122908A1

公开(公告)日：2022-04-21

申请号：US17348936

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk KWON ,  Jiwon SHIN ,  Kwangbok WOO ,  Minseung JI

IPC: H01L23/498 ,  H01L23/32 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.