公开(公告)号：US09538105B2

公开(公告)日：2017-01-03

申请号：US14934718

申请日：2015-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Myung Lee ,  Gun-Hee Han ,  Seog-Heon Ham

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/374 ,  H04N3/14

CPC classification number: H04N5/3575 ,  H04N3/155 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/378

Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

Abstract translation: 公开了一种数字双采样方法，相关的互补金属氧化物半导体（CMOS）图像传感器和包括CMOS图像传感器的数字照相机。 该方法包括响应于复位信号产生对应于像素中显而易见的初始电压电平的第一数字数据，反转第一数字数据，输出对应于从CMOS图像传感器外部接收的图像数据的检测电压，并计数 与等于反相的第一数字数据的初始值开始的时钟信号的同步，以及响应于检测电压的电压电平的时间量。

公开(公告)号：US09898997B2

公开(公告)日：2018-02-20

申请号：US14606282

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hoon Baek ,  Jae-Yoon Sim ,  Dong-Myung Lee ,  Jae-Youl Lee

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2330/06

Abstract: The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.

公开(公告)号：US09514713B2

公开(公告)日：2016-12-06

申请号：US14455484

申请日：2014-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Myung Lee ,  Young-Min Choi ,  Jae-Youl Lee ,  Han-Su Pae ,  Dong-Hoon Baek ,  Young-Hun Lee ,  Kil-Hoon Lee

IPC: G09G3/00 ,  G09G3/20 ,  G09G3/36 ,  H04N5/335 ,  H04N19/70 ,  H03M1/10 ,  A61K31/40 ,  G09G5/18 ,  G09G5/00

CPC classification number: G09G5/18 ,  G09G5/006 ,  G09G2340/02 ,  G09G2370/08

Abstract: A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.

Abstract translation: 提供了具有改进的测试效率的定时控制器，源驱动器和显示驱动器集成电路（DDI）以及操作DDI的方法。 定时控制器包括用于从显示数据生成第一代码的代码生成单元，用于生成包括显示数据和第一代码的数据序列的协议编码器，以及用于通过链接向源驱动器提供数据序列的传输单元 。

公开(公告)号：US10810928B2

公开(公告)日：2020-10-20

申请号：US16168036

申请日：2018-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Wook Lim ,  Dong-Myung Lee ,  Jae-Suk Yu ,  Kil-Hoon Lee ,  Jae-Youl Lee

IPC: G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G3/3275

Abstract: A method of driving a display by communicating with a controller through a first channel and a second channel includes; generating recovery data from a signal received through the first channel during a frame data period, detecting a vertical blank period between frame data periods, checking a training trigger event history during the vertical blank period, and during the vertical blank period, transmitting a training request direct to the first channel through the second channel when there is a training trigger event history.

公开(公告)号：US10355700B2

公开(公告)日：2019-07-16

申请号：US16150347

申请日：2018-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Pil Lim ,  Kyung-Ho Ryu ,  Jae-Suk Yu ,  Jae-Youl Lee ,  Dong-Myung Lee ,  Hyun-Wook Lim

IPC: H03L7/085 ,  H03L7/081 ,  H04L7/04 ,  H03L7/08

Abstract: A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.

公开(公告)号：US09866775B2

公开(公告)日：2018-01-09

申请号：US15372739

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Myung Lee ,  Gun-Hee Han ,  Seog-Heon Ham

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/374 ,  H04N3/14 ,  H04N5/369 ,  H04N5/3745

CPC classification number: H04N5/3575 ,  H04N3/155 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/378

Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.