公开(公告)号：US09898997B2

公开(公告)日：2018-02-20

申请号：US14606282

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hoon Baek ,  Jae-Yoon Sim ,  Dong-Myung Lee ,  Jae-Youl Lee

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2330/06

Abstract: The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.