公开(公告)号：US09959835B2

公开(公告)日：2018-05-01

申请号：US15271837

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Baek ,  Hyunwook Lim ,  Kwi Sung Yoo ,  Eun-Young Jin ,  Kyongho Kim ,  JaeYoul Lee ,  Youngmin Choi

IPC: G09G5/00 ,  H03L7/08 ,  H03L7/089 ,  G09G3/20

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2310/027 ,  G09G2330/10 ,  G09G2370/10 ,  G09G2370/16 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/095

Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

公开(公告)号：US10141963B2

公开(公告)日：2018-11-27

申请号：US15266505

申请日：2016-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwi-Sung Yoo ,  Jae-Youl Lee ,  Hyun-Wook Lim ,  Young-Min Choi ,  Dong-Hoon Baek ,  Kyong-Ho Kim ,  Eun-Young Jin

IPC: H04B1/12 ,  H04L25/03 ,  H04L12/26

Abstract: A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

公开(公告)号：US09898997B2

公开(公告)日：2018-02-20

申请号：US14606282

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hoon Baek ,  Jae-Yoon Sim ,  Dong-Myung Lee ,  Jae-Youl Lee

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2330/06

Abstract: The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.

公开(公告)号：US20170148377A1

公开(公告)日：2017-05-25

申请号：US15358906

申请日：2016-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWI SUNG YOO ,  Dong-Hoon Baek ,  Dong Myung Lee ,  Hyun Wook Lim ,  Eun Young Jin ,  Jae Youl Lee

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G09G3/2092 ,  G09G2310/0221 ,  G09G2370/08 ,  G09G2370/10

Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

公开(公告)号：US09514713B2

公开(公告)日：2016-12-06

申请号：US14455484

申请日：2014-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Myung Lee ,  Young-Min Choi ,  Jae-Youl Lee ,  Han-Su Pae ,  Dong-Hoon Baek ,  Young-Hun Lee ,  Kil-Hoon Lee

IPC: G09G3/00 ,  G09G3/20 ,  G09G3/36 ,  H04N5/335 ,  H04N19/70 ,  H03M1/10 ,  A61K31/40 ,  G09G5/18 ,  G09G5/00

CPC classification number: G09G5/18 ,  G09G5/006 ,  G09G2340/02 ,  G09G2370/08

Abstract: A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.

Abstract translation: 提供了具有改进的测试效率的定时控制器，源驱动器和显示驱动器集成电路（DDI）以及操作DDI的方法。 定时控制器包括用于从显示数据生成第一代码的代码生成单元，用于生成包括显示数据和第一代码的数据序列的协议编码器，以及用于通过链接向源驱动器提供数据序列的传输单元 。