公开(公告)号：US10444619B2

公开(公告)日：2019-10-15

申请号：US15641454

申请日：2017-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Kyoung Lee ,  Il Yong Jang ,  Hwan Seok Seo ,  Byung Gook Kim

IPC: G03F1/32 ,  G03F1/00 ,  G03F1/58 ,  G03F7/00 ,  H01L21/027 ,  H01L21/033

Abstract: A mask blank includes: a light transmitting substrate; a first layer disposed on the light transmitting substrate, and including a chromium compound that contains chromium and at least one element selected from oxygen, nitrogen, and carbon; and a second layer disposed on the first layer as an outermost layer from among the first and second layers, and including a silicon compound that contains silicon and at least one element selected from oxygen, nitrogen, and carbon, an alloy of a transition metal and silicon, or a transition metal and silicon compound that contains a transition metal, silicon, and at least one element selected from oxygen, nitrogen, and carbon. The thickness of the first layer is 45 nm or less, and the thickness of the second layer is 5 nm or greater. An optical density of a stack composed of the first layer and the second layer is 3 or greater.

公开(公告)号：US20170278710A1

公开(公告)日：2017-09-28

申请号：US15411298

申请日：2017-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Seung Moon ,  Byung Gook Kim ,  Jae Hyuck Choi ,  Sung Won Kwon

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  B23K26/126 ,  B23K26/362 ,  B29C59/14 ,  B29C59/16 ,  B29C2791/009 ,  G03F1/80 ,  G03F7/0041 ,  H01L21/02675 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/304 ,  H01L21/30621 ,  H01L21/31138

Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device includes forming a target etching layer on a substrate, patterning the target etching layer to form a pattern layer including a pattern portion having a first height and a first width and a recess portion having a second width, providing a first gas and a second gas on the pattern layer, and performing a reaction process including reacting the first and second gases with a surface of the pattern portion by irradiating a laser beam on the pattern layer. The performing the reaction process includes removing a portion of sidewalls of the pattern portion so that the pattern portion has a third width that is smaller than the first width.

公开(公告)号：US10217635B2

公开(公告)日：2019-02-26

申请号：US15411298

申请日：2017-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Seung Moon ,  Byung Gook Kim ,  Jae Hyuck Choi ,  Sung Won Kwon

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  G03F1/80 ,  B23K26/12 ,  B23K26/362 ,  B29C59/14 ,  H01L21/304 ,  H01L21/02 ,  H01L21/306 ,  B29C59/16 ,  G03F7/004

Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device includes forming a target etching layer on a substrate, patterning the target etching layer to form a pattern layer including a pattern portion having a first height and a first width and a recess portion having a second width, providing a first gas and a second gas on the pattern layer, and performing a reaction process including reacting the first and second gases with a surface of the pattern portion by irradiating a laser beam on the pattern layer. The performing the reaction process includes removing a portion of sidewalls of the pattern portion so that the pattern portion has a third width that is smaller than the first width.

公开(公告)号：US10114555B2

公开(公告)日：2018-10-30

申请号：US15263730

申请日：2016-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sil Wan Chang ,  Byung Gook Kim ,  Jae Young Kwon ,  Jong Youl Lee

IPC: G11C8/00 ,  G06F3/06

Abstract: A semiconductor device includes a memory cell array including a first memory region and a second memory region; a plurality of register sets for storing a plurality of parameter sets; and a control logic circuit configured to, activate a first register set among the plurality of register sets in response to a selection signal, and perform an access operation on the first memory region using a parameter set stored in an activated register set from among the plurality of register sets.