Abstract:
An electroluminescent display and a method of driving the same are disclosed. In one aspect, the display includes a display panel including a plurality of pixels configured to operate based on a first power supply voltage having a negative voltage level. The display panel is configured to generate at least one feedback voltage corresponding to an ohmic drop of the first power supply voltage. An analog-to-digital converter is configured to generate at least one digital feedback signal based on the at least one feedback voltage. An adaptive voltage controller is configured to generate a voltage control signal based on input image data, the at least one digital feedback signal, a distribution of the input image data and the ohmic drop of the first power supply voltage. A voltage converter is configured to generate the first power supply voltage based on an input voltage and the voltage control signal.
Abstract:
A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.
Abstract:
A display apparatus includes: a display panel including a gate line, a storage line adjacent to the gate line, and a pixel, the pixel including a pixel transistor coupled to the gate line, a liquid crystal (“LC”) capacitor coupled to the pixel transistor, and a storage capacitor coupled to the LC capacitor; a first gate driver configured to provide a gate signal to the gate line; and a first level switch configured to provide a storage signal to the storage line, the storage signal being synchronized with the gate signal and having a phase opposite to a phase of the gate signal.
Abstract:
An electroluminescent display and a method of driving the same are disclosed. In one aspect, the display includes a display panel including a plurality of pixels configured to operate based on a first power supply voltage having a negative voltage level. The display panel is configured to generate at least one feedback voltage corresponding to an ohmic drop of the first power supply voltage. An analog-to-digital converter is configured to generate at least one digital feedback signal based on the at least one feedback voltage. An adaptive voltage controller is configured to generate a voltage control signal based on input image data, the at least one digital feedback signal, a distribution of the input image data and the ohmic drop of the first power supply voltage. A voltage converter is configured to generate the first power supply voltage based on an input voltage and the voltage control signal.
Abstract:
A display apparatus includes a display panel and a driving circuit. The display panel includes pixels. Each of the pixels is connected to one of gate lines and one of data lines. The driving circuit drives the gate lines and the data lines to display an image on the display panel. The driving circuit alternately provides a first polarity data driving signal and a second polarity data driving signal to each of the plurality of data lines. During an asymmetrical mode, the first polarity data driving signal is provided to first data lines of the data lines during a first frame period before a blank period begins, and the second polarity data driving signal is provided to the first data lines during a second frame period after the blank period ends. The second frame period excludes the blank period.
Abstract:
A display apparatus includes: a display panel including a gate line, a storage line adjacent to the gate line, and a pixel, the pixel including a pixel transistor coupled to the gate line, a liquid crystal (“LC”) capacitor coupled to the pixel transistor, and a storage capacitor coupled to the LC capacitor; a first gate driver configured to provide a gate signal to the gate line; and a first level switch configured to provide a storage signal to the storage line, the storage signal being synchronized with the gate signal and having a phase opposite to a phase of the gate signal.
Abstract:
A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.
Abstract:
A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.
Abstract:
A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.
Abstract:
A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.