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    Display substrate comprising a plurality of conductive patterns
    1.
    发明授权
    Display substrate comprising a plurality of conductive patterns 有权

    公开(公告)号：US11158656B2

    公开(公告)日：2021-10-26

    申请号：US16569452

    申请日：2019-09-12

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Ji-Sun Kim ,  Ji-Hyun Kim ,  Shin-Il Choi ,  Yeong-Keun Kwon

    IPC: H01L27/12

    Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

    Display substrate
    2.
    发明授权
    Display substrate 有权

    公开(公告)号：US09880432B2

    公开(公告)日：2018-01-30

    申请号：US14528499

    申请日：2014-10-30

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Young-Wan Seo ,  Chong-Chul Chai

    IPC: H01H47/00 ,  H05F3/00 ,  H05F3/02 ,  G02F1/1362 ,  G02F1/1345

    CPC classification number: G02F1/136204 ,  G02F1/13452

    Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

    Scan driver including stage circuit for reducing leakage current
    5.
    发明授权
    Scan driver including stage circuit for reducing leakage current 有权
    扫描驱动器，包括降低漏电流的电路

    公开(公告)号：US09524674B2

    公开(公告)日：2016-12-20

    申请号：US14456976

    申请日：2014-08-11

    Applicant: SAMSUNG DISPLAY CO., LTD. ,  Industry-University Cooperation Foundation Hanyang-University

    Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

    IPC: G06F3/038 ,  G09G5/00 ,  G09G3/32 ,  G11C19/28

    CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

    Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

    Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。

    COUPLING COMPENSATOR FOR DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME
    6.
    发明申请
    COUPLING COMPENSATOR FOR DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME 有权
    用于显示面板的耦合补偿器和包括其的显示装置

    公开(公告)号：US20160240128A1

    公开(公告)日：2016-08-18

    申请号：US14815795

    申请日：2015-07-31

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jong-Hee Kim ,  Jae-Keun Lim ,  Ji-Sun Kim ,  Young-Wan Seo ,  Chong-Chul Chai

    IPC: G09G3/20 ,  G09G3/32

    CPC classification number: G09G3/2007 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2320/0285 ,  G09G2320/0626 ,  G09G2360/16

    Abstract: A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N−1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2.

    Abstract translation: 公开了一种用于显示面板的耦合补偿器和包括耦合补偿器的显示装置。 在一个方面，耦合补偿器包括被配置为接收灰度数据并存储灰阶数据的存储器和被配置为将灰度数据转换成包括第一和第二灰度数据电压的多个灰度数据电压的第一数据转换器。 补偿器还包括耦合电压计算器，其被配置为基于与提供给第（N-1）个像素中的第一组像素的灰度数据相对应的第一灰阶数据电压之间的差计算数据线上产生的线耦合电压， 以及与提供给第N行中的第一组像素的灰度级数据相对应的第二灰度数据电压，其中N是等于或大于2的整数。

    Display device and display apparatus having display devices
    8.
    发明授权
    Display device and display apparatus having display devices 有权

    公开(公告)号：US11551612B2

    公开(公告)日：2023-01-10

    申请号：US17526483

    申请日：2021-11-15

    Applicant: Samsung Display Co., LTD.

    Inventor： Ki Hyun Pyo ,  Bon-Yong Koo ,  Ji-Sun Kim ,  Hyeong Seok Kim

    IPC: G09G3/3233

    Abstract: A display device includes a first pixel circuit, a first scan signal line disposed at a side of the first pixel circuit, extending in a first direction, and transmitting a scan signal; a second pixel circuit disposed at an outermost side of the display device, and a first dummy wire disposed at an outside of the second pixel circuit and extending in the first direction. A width of the first dummy wire is less than a width of the first scan signal line.

    Gate driving circuit and display apparatus including the same
    10.
    发明授权
    Gate driving circuit and display apparatus including the same 有权
    栅极驱动电路及包括其的显示装置

    公开(公告)号：US09524690B2

    公开(公告)日：2016-12-20

    申请号：US14461359

    申请日：2014-08-15

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435

    Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

    Abstract translation: 门驱动电路包括：上拉控制器，响应于前一级之一的进位信号，将先前级之一的进位信号应用于第一节点; 输出时钟信号作为第N栅极输出信号的上拉部分; 输出时钟信号作为第N个进位信号的进位部分; 第一下拉部分，将第一节点处的信号下拉到第二关断电压; 第二下拉部分，将第N栅极输出信号下拉到第一关断电压; 反相部分基于时钟信号和第二截止电压产生反相信号，以将反相信号输出到反相节点; 以及将复位信号输出到反相节点的复位部分。

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