Abstract:
Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.
Abstract:
A display device includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a common electrode, a pixel electrode, a first conductive layer spaced apart from the common electrode, and a second conductive layer disposed on the first conductive layer. The second substrate includes a spacer disposed to overlap with the first conductive layer and the second conductive layer on the first base substrate.
Abstract:
A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.
Abstract:
A display device includes a display panel including a first pixel, a second pixel, and a connection line connecting the first pixel and the second pixel. Each of the first pixel and the second pixel includes a light emitting element, a first transistor including a first electrode, a second electrode electrically connected to the light emitting element, and a gate electrode, a second transistor connected between a first driving voltage line and a connection node and including a gate electrode connected to an emission line, a third transistor connected between a second driving voltage line and the connection node and including a gate electrode connected to the emission line, and a capacitor connected between the gate electrode of the first transistor and the connection node. The connection node of the first pixel is electrically connected to the connection node of the second pixel through the connection line.
Abstract:
A display substrate includes: a pixel circuit including: a switching transistor connected between a first terminal of a compensation capacitor and a data line; and a pixel transistor connected between a second terminal of the compensation capacitor and a first voltage line, the pixel transistor to receive a test voltage; and a test transistor including: a test gate terminal to receive a test signal; a test source terminal electrically connected to the first voltage line; and a test drain terminal electrically connected to the data line.
Abstract:
A display device includes a first pixel circuit, a first scan signal line disposed at a side of the first pixel circuit, extending in a first direction, and transmitting a scan signal; a second pixel circuit disposed at an outermost side of the display device, and a first dummy wire disposed at an outside of the second pixel circuit and extending in the first direction. A width of the first dummy wire is less than a width of the first scan signal line.
Abstract:
A display device includes a display panel including a display and a non-display area, data lines, driving lines, power lines, and pixels connected to said lines being at the display area, a data driver for generating data signals supplied to the pixels, a power supply for generating a power signal supplied to the pixels, and a driving circuit at the non-display area and for generating driving signals supplied to the pixels, the driving circuit including stages for providing the driving signals to at least two of the driving lines, wherein data fan-out lines connected to the data driver are connected to the data lines, a power supply line connected to the power supply is connected to the power lines, and the driving circuit is connected to the driving lines, through a first connection line, a second connection line, a third connection line, and a fourth connection line.
Abstract:
A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.
Abstract:
A thin film transistor array panel includes: a substrate; a gate line and a storage electrode that are disposed on the substrate; a data line that crosses the gate line and storage electrode line; a thin film transistor that is connected with the gate line and data line; and a pixel electrode that is connected to the thin film transistor. The storage electrode includes a first storage electrode that is parallel to the gate line, second storage electrodes that extend on opposing sides of the data line from the first storage electrode, a connection part that crosses the data line and connects pairs of the second storage electrodes, and a connection bridge that crosses the gate line and connects a second storage electrode to a second storage electrode of an adjacent pixel.
Abstract:
A thin film transistor array panel includes: a substrate; a gate line and a storage electrode that are disposed on the substrate; a data line that crosses the gate line and storage electrode line; a thin film transistor that is connected with the gate line and data line; and a pixel electrode that is connected to the thin film transistor. The storage electrode includes a first storage electrode that is parallel to the gate line, second storage electrodes that extend on opposing sides of the data line from the first storage electrode, a connection part that crosses the data line and connects pairs of the second storage electrodes, and a connection bridge that crosses the gate line and connects a second storage electrode to a second storage electrode of an adjacent pixel.