-
公开(公告)号：US11257436B2
公开(公告)日：2022-02-22
申请号：US16922643
申请日：2020-07-07
发明人： Jong Hee Kim
IPC分类号： G09G3/3266 , G11C19/28 , G09G3/36
摘要： Provided are a scan driver and a display device including the same. The scan driver includes a first power line configured to supply a first voltage signal, a second power line configured to supply a second voltage signal having a lower voltage level than the first voltage signal, a pull-up transistor configured to output a corresponding clock signal, among multiple clock signals, as a scan signal in response to a logic state of a first node, a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node, and a first light-blocking film overlapping the pull-up transistor or the pull-down transistor, and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line.
-
2.发明授权公开(公告)号：US09837036B2
公开(公告)日：2017-12-05
申请号：US14862388
申请日：2015-09-23
发明人： Tadashi Amino , Jong Hee Kim , Masataka Kano , Jun Hyun Park
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0417 , G11C19/184 , G11C19/28 , H01L27/124 , H01L27/1255
摘要： A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
-
3.发明授权公开(公告)号：US09685948B2
公开(公告)日：2017-06-20
申请号：US14456926
申请日：2014-08-11
发明人： Jong Hee Kim , Hyun Joon Kim , Kyoung Ju Shin , Alexander Ward , Cheol-Gon Lee , Chong Chul Chai
IPC分类号： G09G3/36 , H03K17/693
CPC分类号： H03K17/693 , G09G3/3677 , G09G2310/0286 , G09G2310/06
摘要： A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.
-
公开(公告)号：US20170032756A1
公开(公告)日：2017-02-02
申请号：US15160922
申请日：2016-05-20
发明人： Jong Hee Kim , Ji Hye Lee , Chong Chul Chai
CPC分类号： G09G3/3677 , G09G3/3648 , G09G3/3674 , G09G3/3696 , G09G2310/08 , G11C19/184 , G11C19/28
摘要： A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.
摘要翻译： 舞台电路包括响应于第一节点的电压，第二节点的电压和第一时钟信号而被配置为向第一输出端子提供进位信号和扫描信号到第二输出端子的输出部分 被提供给第一输入端子的控制器，被配置为响应于提供给第一输入端子的第一时钟信号来控制第二节点的电压的控制器，被配置为响应于控制第一节点的电压的上拉部件 到前一级的进位信号被提供给第二输入端，以及下拉部，被配置为响应于所述第二节点的电压并且提供下一级的进位信号来控制所述第一节点的电压 到第三输入端。
-
公开(公告)号：US20160379566A1
公开(公告)日：2016-12-29
申请号：US15157350
申请日：2016-05-17
发明人： Jae Keun Lim , Jong Hee Kim , Ji-Sun Kim , Young Wan Seo , Chong Chul Chai
IPC分类号： G09G3/3258 , G09G3/3275
CPC分类号： G09G3/3283 , G09G3/3233 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0209
摘要： There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.
摘要翻译： 提供了一种显示装置，包括：显示器，包括连接到第一数据线的第一像素和连接到第二数据线的第二像素;数据信号发生器，被配置为产生输出信号;以及信号分配器， 信号，以产生第一数据信号和第二数据信号，并且分别将第一数据信号和第二数据信号施加到第一数据线和第二数据线，其中数据信号发生器被配置为产生输出 基于形成在第一数据线和第二数据线之间的第一寄生电容的耦合效应以及由第一数据线和第二数据线形成的数据线的寄生电容的耦合效应的信号。
-
公开(公告)号：US20160293269A1
公开(公告)日：2016-10-06
申请号：US14970350
申请日：2015-12-15
发明人： Jae Keun Lim , Jong Hee Kim , Ji Sun Kim , Young Wan Seo , Chong Chul Chai
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3674 , G09G2300/0871 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G11C19/184
摘要： There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each of the plurality of stages includes a first transistor coupled between a first clock input terminal and an output terminal and having a first gate electrode coupled to a first node, a second transistor coupled between the output terminal and a power input terminal and having a second gate electrode coupled to a second clock input terminal, and a third transistor coupled between the first node and a first input terminal configured to receive the start pulse or an output signal of a previous stage of the stages, the third transistor having a third gate electrode coupled to the second clock input terminal.
摘要翻译： 提供了一种移位寄存器，其包括顺序地耦合到被配置为接收起始脉冲的输入端子的多个级，其中多个级中的每一级包括耦合在第一时钟输入端子和输出端子之间的第一晶体管，并且具有第一 耦合到第一节点的第二晶体管，连接在输出端子和电源输入端子之间并具有耦合到第二时钟输入端子的第二栅极电极的第二晶体管，以及耦合在第一节点和配置的第一输入端子之间的第三晶体管 为了接收所述级的前一级的起始脉冲或输出信号，所述第三晶体管具有耦合到所述第二时钟输入端的第三栅极。
-
公开(公告)号：US20160293093A1
公开(公告)日：2016-10-06
申请号：US14952590
申请日：2015-11-25
发明人： Young Wan Seo , Jong Hee Kim , Ji Sun Kim , Jae Keun Lim , Chong Chul Chai
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , G09G2310/0264 , G09G2310/0267 , G09G2310/0275 , G09G2310/0297 , H02M3/073
摘要： A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.
摘要翻译： 解复用器包括：连接在数据输入端和第一输出端之间的第一晶体管; 连接在数据输入端和第二输出端之间的第二晶体管; 以及与所述第一晶体管的栅电极连接的第一预充电电路，所述第一预充电电路包括：并联连接在所述第一晶体管的第一时钟输入端和所述栅电极之间的第三晶体管和第一二极管; 以及连接在第二时钟输入端和第一晶体管的栅电极之间的第一电容器。
-
公开(公告)号：US20160203794A1
公开(公告)日：2016-07-14
申请号：US14991900
申请日：2016-01-08
发明人： Jae Keun Lim , Jong Hee Kim , Chong Chul Chai
CPC分类号： G09G3/3225 , G09G2300/0876 , G09G2310/0216 , G09G2310/08 , G09G2320/045
摘要： A display device includes: a display unit including a plurality of pixels, each of the pixels including: an OLED; and a driving transistor to supply current to an anode of the OLED according to a voltage applied to a gate of the driving transistor and a power supply voltage; a scan driver to supply scan signals to the pixels; an initialization driver to supply initializing signals to the pixels; a data driver to supply data signals to the pixels; light emission drivers to supply first and second light emission signals to the pixels; and a power supply to supply the power supply voltage and an initialization voltage to the pixels, wherein the initialization voltage is supplied to the anode during a first period, and the power supply voltage corresponding to a threshold voltage of the driving transistor is supplied to the gate during a first sub-period of the first period.
摘要翻译： 显示装置包括：包括多个像素的显示单元，每个像素包括：OLED; 以及驱动晶体管，其根据施加到所述驱动晶体管的栅极的电压和电源电压向所述OLED的阳极提供电流; 用于向像素提供扫描信号的扫描驱动器; 初始化驱动器，用于向像素提供初始化信号; 用于向像素提供数据信号的数据驱动器; 发光驱动器，以向像素提供第一和第二发光信号; 以及将电源电压和初始化电压提供给像素的电源，其中在第一时段期间将初始化电压提供给阳极，并且将与驱动晶体管的阈值电压对应的电源电压提供给 在第一个时期的第一个子期间。
-
公开(公告)号：US11823626B2
公开(公告)日：2023-11-21
申请号：US17699943
申请日：2022-03-21
发明人： Jong Hee Kim , Soo Yeon Lee
IPC分类号： G09G3/32 , G09G3/3266 , G09G3/36
CPC分类号： G09G3/3266 , G09G3/3677 , G09G2310/08
摘要： A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.
-
公开(公告)号：US11626077B2
公开(公告)日：2023-04-11
申请号：US17582978
申请日：2022-01-24
发明人： Jong Hee Kim
IPC分类号： G09G3/3266 , G11C19/28
摘要： Provided are a scan driver and a display device including the same. The scan driver includes a first power line configured to supply a first voltage signal, a second power line configured to supply a second voltage signal having a lower voltage level than the first voltage signal, a pull-up transistor configured to output a corresponding clock signal, among multiple clock signals, as a scan signal in response to a logic state of a first node, a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node, and a first light-blocking film overlapping the pull-up transistor or the pull-down transistor, and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line.
-
-
-
-
-
-
-
-
-
搜索结果
39 条记录 (耗时 0.021 秒)
