公开(公告)号：US08902146B2

公开(公告)日：2014-12-02

申请号：US13943931

申请日：2013-07-17

Applicant: Samsung Display Co., Ltd.

Inventor： Beom-Jun Kim ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

IPC: G09G3/38 ,  G02F1/136 ,  G02F1/1343 ,  H01L27/12 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286

Abstract: An array substrate of an LCD having: a gate line formed along a first direction; a data line formed along a second direction crossing the first direction; first and second pixel electrodes spaced apart from each other; a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration.

Abstract translation: 一种LCD的阵列基板，具有沿第一方向形成的栅极线; 沿着与第一方向交叉的第二方向形成的数据线; 第一和第二像素电极彼此间隔开; 薄膜晶体管包括连接到栅极线的栅电极; 源极连接到数据线并部分地与第二像素电极重叠; 以及漏极，其沿着所述第二方向连接到与所述第二像素电极间隔开的所述第一像素电极。 源电极或栅电极与第二像素电极重叠，但漏电极不与第二像素电极重叠。 通过这种配置可以避免第一和第二像素电极之间的电耦合。

公开(公告)号：US20160204136A1

公开(公告)日：2016-07-14

申请号：US14968634

申请日：2015-12-14

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： Noboru TAKEUCHI ,  Min-Soo KANG ,  Beom-Jun Kim ,  Yoon-Ho Kim ,  Seong-Yeol SYN ,  Hong-Woo Lee

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/31 ,  H01L29/49 ,  G09G3/36 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1343 ,  G06F1/04 ,  H01L29/24 ,  G02F1/1368

CPC classification number: H01L29/4966 ,  G09G3/3611 ,  G09G3/3674 ,  G09G3/3696 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28 ,  H01L23/3171 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/495 ,  H01L29/78648 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor and a liquid crystal display device having the same are provided. The transistor includes a first gate electrode disposed on a base substrate; a gate insulating layer disposed on the first gate electrode; a semiconductor layer disposed on the gate insulating layer, and including a channel area; a source electrode and a drain electrode connected to both ends of the semiconductor layer; a passivation layer configured to cover the semiconductor layer, the source electrode, and the drain electrode; and a second gate electrode disposed on the passivation layer, and partially overlapping the channel area in a direction from the drain electrode toward the source electrode.

Abstract translation: 提供了具有该晶体管和液晶显示装置的晶体管。 晶体管包括设置在基底基板上的第一栅电极; 设置在所述第一栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体层，并且包括沟道区域; 源电极和漏电极，连接到半导体层的两端; 被配置为覆盖所述半导体层，所述源电极和所述漏电极的钝化层; 以及设置在所述钝化层上的第二栅极电极，并且在从所述漏极电极朝向所述源极电极的方向上部分地与所述沟道区域重叠。

公开(公告)号：US09207375B2

公开(公告)日：2015-12-08

申请号：US14328277

申请日：2014-07-10

Applicant: Samsung Display Co., Ltd.

Inventor： Sun-Kyu Joo ,  Ju-Hyeon Baek ,  Beom-Jun Kim ,  Yu-Jun Kim ,  Young-Joon Cho

IPC: G02F1/1335 ,  G02B5/20 ,  G02F1/1339

CPC classification number: G02B5/201 ,  G02F1/133514 ,  G02F1/13394 ,  G02F2001/13396

Abstract: A display panel and a liquid crystal display device, in which one of a plurality of color filters is a net-shaped color filter and the other color filters are island-shaped color filters, are provided. According to this approach, a thickness uniformity of the display panel may be achieved.

Abstract translation: 提供了一种显示面板和液晶显示装置，其中多个滤色器中的一个是网状滤色器，并且其它滤色器是岛形滤色器。 根据该方法，可以实现显示面板的厚度均匀性。

公开(公告)号：US10115365B2

公开(公告)日：2018-10-30

申请号：US15231246

申请日：2016-08-08

Applicant: Samsung Display Co., Ltd.

Inventor： Beom-Jun Kim ,  Myung-Koo Hur ,  Bong-Jun Lee ,  Yeon-Kyu Moon ,  Myung-Sub Lee ,  Gyu-Tae Kim

IPC: G09G3/36 ,  G11C19/28 ,  H03K17/693

Abstract: A gate driving circuit including a plurality of stages connected with each other and configured to output a plurality of gate signals. An n-th (n is a natural number) stage including a gate output part including a first transistor connected between a clock signal and an output node outputting an n-th gate signal, the first transistor having a gate electrode connected to a control node, a carry part connected between the clock signal and a carry node outputting an n-th carry signal, a first node control part connected between the output node and a first low voltage, and a second node control part including at least one transistor connected between the control node and a second low voltage different from the first low voltage.