Abstract:
Provided are a scan driver and a display device including the same. The scan driver includes a first power line configured to supply a first voltage signal, a second power line configured to supply a second voltage signal having a lower voltage level than the first voltage signal, a pull-up transistor configured to output a corresponding clock signal, among multiple clock signals, as a scan signal in response to a logic state of a first node, a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node, and a first light-blocking film overlapping the pull-up transistor or the pull-down transistor, and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line.
Abstract:
A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
Abstract:
A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.
Abstract:
A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.
Abstract:
There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.
Abstract:
There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each of the plurality of stages includes a first transistor coupled between a first clock input terminal and an output terminal and having a first gate electrode coupled to a first node, a second transistor coupled between the output terminal and a power input terminal and having a second gate electrode coupled to a second clock input terminal, and a third transistor coupled between the first node and a first input terminal configured to receive the start pulse or an output signal of a previous stage of the stages, the third transistor having a third gate electrode coupled to the second clock input terminal.
Abstract:
A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.
Abstract:
A display device includes: a display unit including a plurality of pixels, each of the pixels including: an OLED; and a driving transistor to supply current to an anode of the OLED according to a voltage applied to a gate of the driving transistor and a power supply voltage; a scan driver to supply scan signals to the pixels; an initialization driver to supply initializing signals to the pixels; a data driver to supply data signals to the pixels; light emission drivers to supply first and second light emission signals to the pixels; and a power supply to supply the power supply voltage and an initialization voltage to the pixels, wherein the initialization voltage is supplied to the anode during a first period, and the power supply voltage corresponding to a threshold voltage of the driving transistor is supplied to the gate during a first sub-period of the first period.
Abstract:
A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.
Abstract:
Provided are a scan driver and a display device including the same. The scan driver includes a first power line configured to supply a first voltage signal, a second power line configured to supply a second voltage signal having a lower voltage level than the first voltage signal, a pull-up transistor configured to output a corresponding clock signal, among multiple clock signals, as a scan signal in response to a logic state of a first node, a pull-down transistor configured to output the second voltage signal from the second power line as the scan signal in response to a logic state of a second node, and a first light-blocking film overlapping the pull-up transistor or the pull-down transistor, and configured to receive the second voltage signal from the second power line and the first voltage signal from the first power line.