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    Integrated circuit comprising a clock tree cell
    3.
    发明授权
    Integrated circuit comprising a clock tree cell 有权
    集成电路包括时钟树单元

    公开(公告)号：US08937505B2

    公开(公告)日：2015-01-20

    申请号：US14134081

    申请日：2013-12-19

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

    IPC: H03K3/01 ,  G05F3/02 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H03K19/177 ,  H01L29/786

    CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

    Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

    Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

    INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL
    4.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL 有权
    包含时钟细胞的集成电路

    公开(公告)号：US20140176228A1

    公开(公告)日：2014-06-26

    申请号：US14134081

    申请日：2013-12-19

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

    Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

    IPC: G05F3/02

    CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

    Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

    Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

    INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL
    5.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL 有权
    包含时钟细胞的集成电路

    公开(公告)号：US20140176216A1

    公开(公告)日：2014-06-26

    申请号：US14134167

    申请日：2013-12-19

    Applicant: Commissariat à I'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

    Inventor： Yvain Thonnart ,  Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel

    IPC: H03K3/012 ,  H01L27/12 ,  G05F3/02

    CPC classification number: H03K3/012 ,  G05F3/02 ,  G06F1/10 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648

    Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).

    Abstract translation: 本发明涉及一种集成电路，包括：块，包括：第一（38）和第二（40）相对掺杂的半导体阱; 时钟树单元（30）包括：标准单元（42,43），其彼此相邻放置，每个标准单元（42）包括第一晶体管（60,62）和由标准单元包围的时钟树单元（30） 具有与所述第一阱（38）的掺杂相同的掺杂类型的第三半导体阱（104）; 第二晶体管（100,102）; 围绕第三阱（104）连续延伸的半导体条（106），并且具有与第三阱的掺杂相反的掺杂类型，从而将第三阱（104）与第一阱（38）电隔离。

    METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT
    6.
    发明申请
    METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT 有权
    控制集成电路的方法

    公开(公告)号：US20140292374A1

    公开(公告)日：2014-10-02

    申请号：US14225520

    申请日：2014-03-26

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

    IPC: H03K19/00 ,  H03K19/0185

    CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

    Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

    Method for controlling an integrated circuit
    7.
    发明授权
    Method for controlling an integrated circuit 有权
    控制集成电路的方法

    公开(公告)号：US09479168B2

    公开(公告)日：2016-10-25

    申请号：US14225520

    申请日：2014-03-26

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

    IPC: H03K19/096 ,  H03K19/00 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H03K19/0185

    CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

    Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

    Ionizing radiation detector
    8.
    发明授权
    Ionizing radiation detector 有权

    公开(公告)号：US11131782B2

    公开(公告)日：2021-09-28

    申请号：US16677005

    申请日：2019-11-07

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Gilles Gasiot ,  Fady Abouzeid

    IPC: G01T1/24 ,  H01L27/07 ,  H01L31/103

    Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

    PULSED SEMI-DYNAMIC FAST FLIP-FLOP WITH SCAN
    10.
    发明申请
    PULSED SEMI-DYNAMIC FAST FLIP-FLOP WITH SCAN 审中-公开

    公开(公告)号：US20180212596A1

    公开(公告)日：2018-07-26

    申请号：US15414419

    申请日：2017-01-24

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Patrik Temleitner ,  Fady Abouzeid

    IPC: H03K3/356 ,  H03K19/21

    CPC classification number: H03K19/215 ,  H03K3/012 ,  H03K3/356173

    Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

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