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公开(公告)号：US20160162200A1
公开(公告)日：2016-06-09
申请号：US14868211
申请日：2015-09-28
Inventor： Won-Gyu SHIN , Jung-Whan CHOI , Lee-Sup KIM , Young-Suk MOON , Yong-Kee KWON
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0658 , G06F3/0673 , G06F12/08 , G06F13/1636 , G06F13/1689 , G11C11/40611 , G11C11/4094
Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.
Abstract translation: 存储器控制器包括参照每个请求的定时参数值来决定从外部设备提供的多个请求的处理顺序的调度器; 以及定时控制电路，其根据对应的地址调整定时参数值以访问存储器设备，所述相应地址用于处理所述多个请求的相应请求。
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公开(公告)号：US20160231961A1
公开(公告)日：2016-08-11
申请号：US14885902
申请日：2015-10-16
Inventor： Won-Gyu SHIN , Jung-Whan CHOI , Lee-Sup KIM , Young-Suk MOON , Yong-Kee KWON
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F12/0215 , G06F12/123
Abstract: A memory controller includes a request queue that stores requests provided from an external device, a scheduler that calculates a score for each request included in the request queue and determines a processing order of the requests based on the scores for the requests, and a weight generation circuit that generates a weight vector including weights used to calculated the scores.
Abstract translation: 存储器控制器包括：存储从外部设备提供的请求的请求队列;调度器，其计算包含在所述请求队列中的每个请求的分数，并基于所述请求的得分确定所述请求的处理顺序;以及权重生成 电路，其产生包括用于计算分数的权重的权重向量。
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公开(公告)号：US20190164605A1
公开(公告)日：2019-05-30
申请号：US16007659
申请日：2018-06-13
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Jung-Hyun KWON , Do-Sun HONG , Won-Gyu SHIN
Abstract: A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.
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公开(公告)号：US20190164604A1
公开(公告)日：2019-05-30
申请号：US16007598
申请日：2018-06-13
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Jung-Hyun KWON , Do-Sun HONG , Won-Gyu SHIN
CPC classification number: G11C13/0069 , G06F13/4068 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C13/0061
Abstract: A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.
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5.发明申请公开(公告)号：US20200372954A1
公开(公告)日：2020-11-26
申请号：US16993787
申请日：2020-08-14
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Jung-Hyun KWON , Won-Gyu SHIN , Do-Sun HONG
Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190189204A1
公开(公告)日：2019-06-20
申请号：US16124882
申请日：2018-09-07
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Won-Gyu SHIN , Jung-Hyun KWON , Do-Sun HONG
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/0035 , G11C13/0069
Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.
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7.发明申请公开(公告)号：US20190146871A1
公开(公告)日：2019-05-16
申请号：US16029083
申请日：2018-07-06
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Do-Sun HONG , Jung-Hyun KWON , Won-Gyu SHIN
IPC: G06F11/10 , G11C29/52 , G06F3/06 , G06F12/1009
Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.
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公开(公告)号：US20190237150A1
公开(公告)日：2019-08-01
申请号：US16124927
申请日：2018-09-07
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Jung-Hyun KWON , Do-Sun HONG , Won-Gyu SHIN
Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.
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9.发明申请公开(公告)号：US20190130972A1
公开(公告)日：2019-05-02
申请号：US16029088
申请日：2018-07-06
Applicant: SK hynix Inc.
Inventor： Seung-Gyu JEONG , Jung-Hyun KWON , Won-Gyu SHIN , Do-Sun HONG
Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.
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公开(公告)号：US20190065115A1
公开(公告)日：2019-02-28
申请号：US15980238
申请日：2018-05-15
Applicant: SK hynix Inc.
Inventor： Jung-Hyun KWON , Do-Sun HONG , Won-Gyu SHIN
Abstract: A memory system includes: a memory controller; and a plurality of memory devices each of which includes a plurality of input pads, where signals of different input pads are set as valid signals, wherein when the memory controller transfers a mask command to the memory devices and one or more valid signals among the valid signals of the memory devices are enabled along with the mask command, commands of a first kind among commands that are transferred to the memory devices from the memory controller after the mask command are implemented in one or more memory devices which correspond to the enabled one or more valid signals.
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