MEMORY CONTROLLER
    2.
    发明申请
    MEMORY CONTROLLER 有权
    内存控制器

    公开(公告)号:US20160231961A1

    公开(公告)日:2016-08-11

    申请号:US14885902

    申请日:2015-10-16

    Abstract: A memory controller includes a request queue that stores requests provided from an external device, a scheduler that calculates a score for each request included in the request queue and determines a processing order of the requests based on the scores for the requests, and a weight generation circuit that generates a weight vector including weights used to calculated the scores.

    Abstract translation: 存储器控制器包括:存储从外部设备提供的请求的请求队列;调度器,其计算包含在所述请求队列中的每个请求的分数,并基于所述请求的得分确定所述请求的处理顺序;以及权重生成 电路,其产生包括用于计算分数的权重的权重向量。

    APPARATUS AND METHOD WITH MULTI-TASK PROCESSING

    公开(公告)号:US20230131543A1

    公开(公告)日:2023-04-27

    申请号:US17903969

    申请日:2022-09-06

    Abstract: A processor-implemented method with multi-task processing includes: obtaining weights of a first neural network; obtaining first delta weights of a second neural network that is fine-tuned from the first neural network, based on a target task; performing an operation of the second neural network on first input data, based on sums of the weights of the first neural network and the first delta weights; obtaining second delta weights of a third neural network that is fine-tuned from the first neural network, based on a change of the target task; replacing the first delta weights with the second delta weights; and performing an operation of the third neural network on second input data, based on sums of the weights of the first neural network and the second delta weights, wherein the first delta weights comprise difference values in the weights of the first neural network and weights of the second neural network, and the second delta weight comprises difference values in the weights of the first neural network and weights of the third neural network.

    DATA SIGNAL RECEIVER, TRANSCEIVER SYSTEM AND METHOD OF RECEIVING DATA SIGNAL
    5.
    发明申请
    DATA SIGNAL RECEIVER, TRANSCEIVER SYSTEM AND METHOD OF RECEIVING DATA SIGNAL 有权
    数据信号接收器,收发器系统和接收数据信号的方法

    公开(公告)号:US20150280698A1

    公开(公告)日:2015-10-01

    申请号:US14666988

    申请日:2015-03-24

    Abstract: A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal.

    Abstract translation: 数据信号接收器包括时钟信号滤波器,下降脉冲信号发生器,混合块和采样器。 时钟信号滤波器通过对时钟信号进行滤波来产生第一滤波时钟信号和第二滤波时钟信号。 下降脉冲信号发生器基于第一滤波时钟信号产生下降脉冲信号。 混合块通过混合数据信号和下降脉冲信号来产生混合数据信号。 采样器通过响应于第二滤波时钟信号对混合数据信号进行采样而产生恢复的数据信号。

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