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公开(公告)号：US10146443B2
公开(公告)日：2018-12-04
申请号：US14868211
申请日：2015-09-28
Inventor： Won-Gyu Shin , Jung-Whan Choi , Lee-Sup Kim , Young-Suk Moon , Yong-Kee Kwon
Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.
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公开(公告)号：US09792065B2
公开(公告)日：2017-10-17
申请号：US14885902
申请日：2015-10-16
Inventor： Won-Gyu Shin , Jung-Whan Choi , Lee-Sup Kim , Young-Suk Moon , Yong-Kee Kwon
IPC: G06F12/00 , G06F3/06 , G06F12/02 , G06F12/123
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F12/0215 , G06F12/123
Abstract: A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.
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公开(公告)号：US10818365B2
公开(公告)日：2020-10-27
申请号：US16124927
申请日：2018-09-07
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Do-Sun Hong , Won-Gyu Shin
Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.
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公开(公告)号：US10559354B2
公开(公告)日：2020-02-11
申请号：US16007538
申请日：2018-06-13
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Do-Sun Hong , Won-Gyu Shin
Abstract: A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.
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公开(公告)号：US11216335B2
公开(公告)日：2022-01-04
申请号：US16683989
申请日：2019-11-14
Applicant: SK hynix Inc.
Inventor： Won-Gyu Shin
Abstract: A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10762008B2
公开(公告)日：2020-09-01
申请号：US16203591
申请日：2018-11-28
Applicant: SK hynix Inc.
Inventor： Jung-Hyun Kwon , Do-Sun Hong , Won-Gyu Shin , Seung-Gyu Jeong
Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.
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公开(公告)号：US11003531B2
公开(公告)日：2021-05-11
申请号：US16038792
申请日：2018-07-18
Applicant: SK hynix Inc.
Inventor： Jung-Hyun Kwon , Do-Sun Hong , Seung-Gyu Jeong , Won-Gyu Shin
Abstract: A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.
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公开(公告)号：US10853169B2
公开(公告)日：2020-12-01
申请号：US16029083
申请日：2018-07-06
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Do-Sun Hong , Jung-Hyun Kwon , Won-Gyu Shin
Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.
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公开(公告)号：US10529421B2
公开(公告)日：2020-01-07
申请号：US16007659
申请日：2018-06-13
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Do-Sun Hong , Won-Gyu Shin
Abstract: A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.
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公开(公告)号：US10777274B2
公开(公告)日：2020-09-15
申请号：US16029088
申请日：2018-07-06
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Won-Gyu Shin , Do-Sun Hong
Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.
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