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    Memory system, memory controller, and operation method of memory system
    1.
    发明授权
    Memory system, memory controller, and operation method of memory system 有权

    公开(公告)号：US11307794B2

    公开(公告)日：2022-04-19

    申请号：US17095175

    申请日：2020-11-11

    Applicant: SK hynix Inc.

    Inventor： Seung Gu Ji ,  Hyung Min Lee

    IPC: G06F3/06

    Abstract: Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.

    Apparatus and method for recovering a data error in a memory system
    2.
    发明授权
    Apparatus and method for recovering a data error in a memory system 有权

    公开(公告)号：US11245420B2

    公开(公告)日：2022-02-08

    申请号：US17062958

    申请日：2020-10-05

    Applicant: SK hynix Inc.

    Inventor： Dae Sung Kim ,  Seung Gu Ji

    IPC: H03M13/11 ,  G06F11/10

    Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.

    Data storage device and operating method thereof
    5.
    发明授权
    Data storage device and operating method thereof 有权

    公开(公告)号：US10963339B2

    公开(公告)日：2021-03-30

    申请号：US16591272

    申请日：2019-10-02

    Applicant: SK hynix Inc.

    Inventor： Seung Gu Ji ,  Hyun Jun Lee ,  Byeong Gyu Park

    IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  H03K19/21

    Abstract: Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.

    Memory system with priority processing and operating method thereof
    7.
    发明授权
    Memory system with priority processing and operating method thereof 有权

    公开(公告)号：US10346052B2

    公开(公告)日：2019-07-09

    申请号：US15837664

    申请日：2017-12-11

    Applicant: SK hynix Inc.

    Inventor： Seung Gu Ji ,  Duck Hoi Koo

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F13/18

    Abstract: A memory system includes a nonvolatile memory device; and a controller suitable for processing a write request of first data transmitted from a host device. The controller includes a first processing circuit suitable for generating a read command afforded with a priority, based on the write request; and a second processing circuit suitable for processing the read command according to the priority and thereby reading second data including old data of the first data from the nonvolatile memory device.

    Storage device and method for foggy and fine programming
    8.
    发明授权
    Storage device and method for foggy and fine programming 有权

    公开(公告)号：US11797202B2

    公开(公告)日：2023-10-24

    申请号：US16918521

    申请日：2020-07-01

    Applicant: SK hynix Inc.

    Inventor： Seung Gu Ji ,  Jun Rye Rho

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

    Memory controller for performing unmap operation and memory system having the same
    9.
    发明授权
    Memory controller for performing unmap operation and memory system having the same 有权

    公开(公告)号：US10977170B2

    公开(公告)日：2021-04-13

    申请号：US16150716

    申请日：2018-10-03

    Applicant: SK hynix Inc.

    Inventor： Byeong Gyu Park ,  Seung Gu Ji

    IPC: G06F12/02 ,  G06F3/06

    Abstract: The memory controller includes an unmap controller configured to receive unmap information from a host, calculate operation times required to perform a plurality of respective unmap operations based on the unmap information, and output an unmap command for an unmap operation having a relatively short operation time among the plurality of unmap operations as a result of the calculation; a buffer memory configured to store a plurality of types of address mapping information; and a control processor configured to control the unmap controller and the buffer memory in response to a command received from the host.

    STORAGE DEVICE AND OPERATING METHOD THEREOF
    10.
    发明申请
    STORAGE DEVICE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20200319961A1

    公开(公告)日：2020-10-08

    申请号：US16683715

    申请日：2019-11-14

    Applicant: SK hynix Inc.

    Inventor： Seung Gu Ji ,  Byeong Gyu Park

    IPC: G06F11/10 ,  G06F3/06

    Abstract: The memory controller is provided to include: an operation controller configured to control memory devices to read first to third source pages and a source parity page in a source stripe and perform program operations on first to third target pages and a target parity page in a target stripe, a program data determiner configured to determine first to third program data to be programmed in the first to third target pages and to determine data read successfully from the first and second source pages as the first and second program data and determine recovery data as the third program data upon whether the read operation for the third source page has failed, and a parity calculator configured to generate calculation data by using the first and second program data, and generate the recovery data by using source parity data and the calculation data.

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