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公开(公告)号：US10747660B2
公开(公告)日：2020-08-18
申请号：US16055680
申请日：2018-08-06
Applicant: SK hynix Inc.
Inventor： Seung Gu Ji , Chung Un Na , Byeong Gyu Park
Abstract: A memory system includes a plurality of memory devices, each including a plurality of memory blocks; and a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.
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公开(公告)号：US11789650B2
公开(公告)日：2023-10-17
申请号：US17327310
申请日：2021-05-21
Applicant: SK hynix Inc.
Inventor： Chung Un Na
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: The present technology relates to an electronic device. According to the present technology, a storage device includes a memory device configured to include memory cells for storing data and circuitry structured to generate voltage information indicating whether a voltage used for performing an operation on the memory cells is included in a preset voltage range; and a memory controller in communication with the memory device and configured to transmit, to the memory device, a status command requesting for a status response indicating a status of the operation, and control the memory device to change a voltage used for performing the operation based on the status response provided from the memory device and including the voltage information.
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公开(公告)号：US11861223B2
公开(公告)日：2024-01-02
申请号：US17365160
申请日：2021-07-01
Applicant: SK hynix Inc.
Inventor： Chung Un Na
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/064 , G06F3/0605 , G06F3/0652 , G06F3/0679
Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller for storing a first read command generated in response to a read request and a first physical address in the first read command queue; and a command schedule controller for searching for a first physical address group including at least one second physical address including a page number equal to that of the physical address among the physical addresses stored in the first read command queue and the first physical address, in response to a scheduling event signal provided from the command generation controller.
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公开(公告)号：US11133068B2
公开(公告)日：2021-09-28
申请号：US16878371
申请日：2020-05-19
Applicant: SK hynix Inc.
Inventor： Chung Un Na
IPC: G06F12/0882 , G11C16/26 , G11C7/10 , G11C16/14 , G06F9/4401 , G06F11/30
Abstract: A memory system includes: a memory device including a memory cell array and a page buffer circuit, the memory device performing a data program operation or a data erase operation, suspending the data program operation or the data erase operation in response to a suspend command, performing a data read operation of storing read data from the memory cell array in the page buffer circuit in response to a read command, and performing a data output operation of outputting the read data stored in the page buffer circuit; and a memory controller outputting a pre-resume command to the memory device between a first time at which the data read operation is complete and a second time at which the data output operation starts.
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5.发明授权公开(公告)号：US11734178B2
公开(公告)日：2023-08-22
申请号：US17358922
申请日：2021-06-25
Applicant: SK hynix Inc.
Inventor： Chung Un Na
IPC: G06F12/08 , G06F12/0844 , G06F12/02
CPC classification number: G06F12/0844 , G06F12/0253 , G06F2212/608 , G06F2212/7205
Abstract: A storage device includes: a memory device including a plurality of planes, and a plurality of cache buffers and data buffers; and a memory controller for controlling the memory device to transmit first data and second data from first plane and second plane into the respective first cache buffer and second cache buffer, and control the first cache buffer and the second cache buffer to transmit the first data and the second data to the memory controller. In response to a read request for third data from a host while the first data is transmitting from the first cache buffer to the memory controller, the memory controller transmits a cache read command to the memory device such that the memory device reads the third data after the first data is completely transmitted to the memory controller, before the second data is transmitted from the second cache buffer.
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Patent Agency Ranking
公开(公告)号：US11355215B2
公开(公告)日：2022-06-07
申请号：US17149578
申请日：2021-01-14
Applicant: SK hynix Inc.
Inventor： Chung Un Na
Abstract: A data storage apparatus may include a data storage device including at least one data die to store first data, and at least one parity die to store second data, third data, and a chip-kill parity, where the at least one data die and the at least one parity die are connected to a channel, and controller in communication with the data storage device and configured to receive a write request for the first data and the second data from a host that is in communication with the data storage device through the channel to generate the chip-kill parity from the first data and the second data. The controller is further configured to read the third data from the parity die and provide the third data to the host upon receipt of a read request for the third data from the host while the chip-kill parity is being updated based on the first data.
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公开(公告)号：US12056367B2
公开(公告)日：2024-08-06
申请号：US17563895
申请日：2021-12-28
Applicant: SK hynix Inc.
Inventor： Chung Un Na , Sang Sik Kim
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0658 , G06F3/0679
Abstract: A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.
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公开(公告)号：US11775223B2
公开(公告)日：2023-10-03
申请号：US17945230
申请日：2022-09-15
Applicant: SK hynix Inc.
Inventor： Chung Un Na
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/064 , G06F3/0604 , G06F3/0652 , G06F3/0679
Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.
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公开(公告)号：US11507322B2
公开(公告)日：2022-11-22
申请号：US17365185
申请日：2021-07-01
Applicant: SK hynix Inc.
Inventor： Chung Un Na
IPC: G06F3/06
Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.
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公开(公告)号：US11437113B2
公开(公告)日：2022-09-06
申请号：US16876407
申请日：2020-05-18
Applicant: SK hynix Inc.
Inventor： Min Hwan Moon , Chung Un Na
IPC: G11C29/38 , G06F12/0804
Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.
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