公开(公告)号：US09870813B2

公开(公告)日：2018-01-16

申请号：US14863092

申请日：2015-09-23

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： G11C11/40 ,  G11C11/4076 ,  G11C7/10

CPC分类号： G11C11/4076 ,  G11C7/109

摘要： A semiconductor device includes: a command decoding unit suitable for decoding external command signals to generate an internal command signal; and a pulse control unit suitable for controlling a pulse width of the internal command signal.

公开(公告)号：US09576629B2

公开(公告)日：2017-02-21

申请号：US14030697

申请日：2013-09-18

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： G06F12/00 ,  G11C7/24 ,  G11C7/20 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C7/24 ,  G06F12/023 ,  G11C7/20 ,  G11C29/785 ,  G11C2029/0401 ,  G11C2029/4402

摘要： A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array, an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit, and an output circuit suitable for outputting the available capacity information.

摘要翻译： 存储器件包括具有多个存储器单元的存储单元阵列，适用于存储与存储单元阵列中的故障存储单元相对应的故障地址的存储单元，适用于产生指示存储单元阵列的可用容量信息的可用存储容量确定单元 存储单元中的可用存储容量，以及适于输出可用容量信息的输出电路。

公开(公告)号：US09406360B2

公开(公告)日：2016-08-02

申请号：US14489120

申请日：2014-09-17

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C29/02

CPC分类号： G11C7/222 ,  G11C7/1087 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

摘要： A semiconductor device may include a first pad suitable for inputting a dock, a plurality of second pads suitable for inputting data through a plurality of first data paths, a third pad suitable for inputting a first strobe signal through a first strobe signal path, a data latch unit suitable for latching the data inputted through the first data paths in response to the first strobe signal inputted through the first strobe signal path, and a calibration control unit suitable for calibrating delay values of the plurality of first data paths and the first strobe signal path in a first calibration mode such that a plurality of first test signals passing through the respective first data paths and a second test signal passing through the first strobe path are in phase with the clock inputted from the first pad.

摘要翻译： 半导体器件可以包括适于输入基座的第一焊盘，适用于通过多个第一数据路径输入数据的多个第二焊盘，适于通过第一选通信号路径输入第一选通信号的第三焊盘，数据 锁存单元，用于响应于通过第一选通信号路径输入的第一选通信号，锁存通过第一数据路径输入的数据;以及校准控制单元，适于校准多个第一数据路径的延迟值和第一选通信号 路径，使得通过各个第一数据路径的多个第一测试信号和通过第一选通路径的第二测试信号与从第一焊盘输入的时钟同相。

公开(公告)号：US09311986B2

公开(公告)日：2016-04-12

申请号：US14469072

申请日：2014-08-26

申请人： SK hynix Inc.

发明人： Chang-Hyun Kim ,  Choung-Ki Song

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C7/02

CPC分类号： G11C11/40626 ,  G11C7/02 ,  G11C11/40615

摘要： A semiconductor memory device includes a control signal generator suitable for generating a control signal corresponding to temperature information, a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to a refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal, and a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.

摘要翻译： 半导体存储器件包括适于产生对应于温度信息的控制信号的控制信号发生器，适于在预定时刻响应于刷新命令信号启用用于智能刷新操作的刷新信号的刷新控制器，并使能刷新信号 用于响应于刷新命令信号在对应于控制信号的时刻进行正常的刷新操作，以及适于存储数据并响应于刷新刷新信号执行智能刷新操作和正常刷新操作的数据存储 控制器。

公开(公告)号：US09275716B2

公开(公告)日：2016-03-01

申请号：US13719906

申请日：2012-12-19

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： G11C7/00 ,  G11C11/402 ,  G11C7/20 ,  G11C11/406 ,  G11C7/02 ,  G11C11/408

CPC分类号： G11C11/402 ,  G11C7/02 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4096 ,  G11C2211/4065

摘要： A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

摘要翻译： 存储器包括被配置为包括连接到多个字线的多个第一存储器单元的第一单元阵列，被配置为包括连接到所述多个字线的多个第二存储单元的第二单元阵列，其中， 连接到对应字线的多个第二存储单元存储对应字线的激活次数，以及激活号码更新单元，被配置为更新存储在连接到所述多个第二存储器单元的对应组中的值 激活的多个字线的字线。

公开(公告)号：US09190138B2

公开(公告)日：2015-11-17

申请号：US14293694

申请日：2014-06-02

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： G11C5/02 ,  G11C11/406 ,  G11C11/408 ,  G11C7/02

CPC分类号： G11C11/40618 ,  G11C5/025 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C11/4087

摘要： A semiconductor memory device includes a first bank, a second bank disposed separately from the first bank along a first direction, a third bank disposed separately from the first bank along a second direction substantially perpendicular to the first direction, a fourth bank disposed separately from the second bank along the second direction and from the third bank along the first direction, a first row control region, which is disposed between the first bank and the second bank, suitable for controlling a row decoding operation of the first bank and the second bank, a second row control region, which is disposed between the third bank and the fourth bank, suitable for controlling a row decoding operation of the third bank and the fourth bank, and a refresh control unit suitable for controlling a refresh operation of the first to fourth banks.

摘要翻译： 半导体存储器件包括第一组，沿第一方向与第一组分离设置的第二组，沿着基本上垂直于第一方向的第二方向与第一组分开设置的第三组，与第一组分开设置的第四组， 沿着第二方向的第二组和沿着第一方向的第三组，布置在第一组和第二组之间的第一行控制区，适于控制第一组和第二组的行解码操作， 布置在第三组和第四组之间的适于控制第三组和第四组的行解码操作的第二行控制区，以及适于控制第一至第四组的刷新操作的刷新控制单元 银行。

公开(公告)号：US09140741B2

公开(公告)日：2015-09-22

申请号：US13720191

申请日：2012-12-19

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： G06F11/00 ,  G01R31/30 ,  G01R31/04 ,  G11C29/00 ,  G11C29/12 ,  G11C29/48

CPC分类号： G01R31/041 ,  G01R31/046 ,  G11C29/00 ,  G11C29/1201 ,  G11C29/48

摘要： An integrated circuit chip includes a plurality of test input pads configured to receive a plurality of test input signals, a plurality of single-ended type buffers configured to receive signals input to the plurality of test input pads in a connectivity test mode, a plurality of differential-type buffers configured to receive signals input to the plurality of test input pads in a normal mode, a signal combination unit configured to combine the plurality of test input signals input through the plurality of single-ended type buffers, and to generate a plurality of test output signals, and a plurality of test output pads configured to output the plurality of test output signals in the connectivity test mode.

摘要翻译： 集成电路芯片包括被配置为接收多个测试输入信号的多个测试输入焊盘，多个单端型缓冲器，被配置为在连接测试模式下接收输入到多个测试输入焊盘的信号，多个 差分型缓冲器，其被配置为以正常模式接收输入到所述多个测试输入焊盘的信号;信号组合单元，被配置为组合通过所述多个单端型缓冲器输入的所述多个测试输入信号，并且生成多个 的测试输出信号，以及多个测试输出焊盘，被配置为在连接测试模式下输出多个测试输出信号。

公开(公告)号：US09123406B2

公开(公告)日：2015-09-01

申请号：US14293649

申请日：2014-06-02

申请人： SK hynix Inc.

发明人： Yo-Sep Lee ,  Chang-Hyun Kim ,  Choung-Ki Song

IPC分类号： G11C8/18 ,  G11C8/08 ,  G11C8/06 ,  G11C8/10

CPC分类号： G11C8/18

摘要： A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.

摘要翻译： 半导体存储器件包括：时钟信号生成单元，适于分割外部时钟信号以产生对应于外部时钟信号的奇数周期的第一内部时钟信号和对应于偶数周期的第二内部时钟;第一输入单元， 用于响应于第一内部时钟信号接收外部命令信号和外部地址信号，第二输入单元适于响应于第二内部时钟信号接收外部命令信号和外部地址信号;以及操作控制单元 适于在减速模式期间启用第一输入单元和第二输入单元中的一个并禁用第一输入单元和第二输入单元中的另一个。

公开(公告)号：US09070428B2

公开(公告)日：2015-06-30

申请号：US14090945

申请日：2013-11-26

申请人： SK hynix Inc.

发明人： Hye-Young Lee ,  Kie-Bong Ku ,  Choung-Ki Song ,  Sung-Hwa Ok ,  Se-Jin Yoo

IPC分类号： G11C8/18 ,  G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/105

摘要： A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.

摘要翻译： 半导体器件包括耦合到彼此电绝缘的第一和第二数据线的第一和第二组组。 该半导体器件包括适于在特定模式中向第二数据线提供预定数据的寄存器单元，适于外部输出加载到第二数据线上的预定数据的数据传输和输出单元，并同时将预定数据传送到第一数据线 数据线，以及适于在特定模式中外加输出加载到第一数据线上的预定数据的数据输出单元。

公开(公告)号：US08947132B2

公开(公告)日：2015-02-03

申请号：US14090858

申请日：2013-11-26

申请人： SK hynix Inc.

发明人： Choung-Ki Song

IPC分类号： H03B1/00 ,  H03K3/00 ,  G05F3/08

CPC分类号： G11C29/12005 ,  G01R31/31701 ,  G11C11/40

摘要： A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

摘要翻译： 半导体器件包括能够产生正常代码的正常代码生成单元，能够存储响应于测试控制信号输出测试代码的多个初步测试代码的测试代码输出单元，以及能够 在正常操作模式下产生正常参考电压，并响应于正常代码和测试代码在测试操作模式中产生测试参考电压。