公开(公告)号：US09536846B2

公开(公告)日：2017-01-03

申请号：US14526073

申请日：2014-10-28

Applicant: SK hynix Inc.

Inventor： Jin Woo Park ,  Sung Su Park ,  Bae Yong Kim

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05138 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/012

Abstract: A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Abstract translation: 一种半导体器件包括：芯片本体，具有包括彼此不同的至少两个区域的不平坦表面;穿透芯片本体并具有由芯片体的不平坦表面露出的端部的贯通电极，设置有钝化层 并且设置在钝化层和通孔的露出端上并与芯片体的不平坦表面重叠的凸起。

公开(公告)号：US10109545B2

公开(公告)日：2018-10-23

申请号：US15459592

申请日：2017-03-15

Applicant: SK hynix Inc.

Inventor： Jong Kyu Moon ,  Jong Hoon Kim ,  Sung Su Park

IPC: H01L23/26 ,  H01L21/304 ,  H01L21/306 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L21/683

Abstract: Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.

公开(公告)号：US09158081B2

公开(公告)日：2015-10-13

申请号：US14089487

申请日：2013-11-25

Applicant: SK HYNIX INC.

Inventor： Tae Ho Jo ,  Taek Joong Kim ,  Wan Choon Park ,  Sung Su Park

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/43

CPC classification number: G02B6/43 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor package includes a substrate and an optical communication part. A first chip stack part and a second chip stack part are disposed over the substrate and are separate from each other, and the optical communication part is disposed in a cavity formed in the substrate to provide an optical signal path between the first and second chip stack parts.

Abstract translation: 半导体封装包括基板和光通信部。 第一芯片堆叠部分和第二芯片堆叠部分设置在基板上并且彼此分离，并且光通信部分设置在形成在基板中的空腔中，以在第一和第二芯片堆叠之间提供光信号路径 部分。