公开(公告)号：US20240085282A1

公开(公告)日：2024-03-14

申请号：US18454381

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Chul JO ,  Sang Hyun PARK ,  Su Jin SHIN ,  Gil Ho GU ,  Dae Gon YU ,  So Yeon LEE ,  Yun Bin JEONG

IPC: G01N1/32 ,  B24B7/22

CPC classification number: G01N1/32 ,  B24B7/228

Abstract: There is provide a method for manufacturing analytical semiconductor samples by using an apparatus for manufacturing analytical semiconductor samples, which minimizes a feedback time by manufacturing a viewing surface that is environment-friendly and has a large area. The method comprising mounting the analytical semiconductor samples to a holder; discharging deionized (DI) water to an upper surface of a polishing plate through a DI water nozzle; grinding the analytical semiconductor samples with the upper surface of the polishing plat; determining whether a desired viewing surface of the analytical semiconductor samples has been acquired after the grinding of the analytical semiconductor samples; and transferring the analytical semiconductor samples to analyze the viewing surface of the ground analytical semiconductor samples based on a determination that the desired viewing surface of the analytical semiconductor samples has been acquired.

公开(公告)号：US20230101674A1

公开(公告)日：2023-03-30

申请号：US17718754

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS Co., LTD.

Inventor： Youn Gon OH ,  Ji Hun KIM ,  SaeYun KO ,  Gil Ho GU ,  Dong Su KIM ,  Eun Hee LEE ,  Ho Chan LEE ,  Seong Sil JEONG ,  Seong Pyo HONG

IPC: H01L21/673 ,  H01L21/66

Abstract: Provided is a tray including a plate including a first region and a second region, a first groove on the first region of the plate and to which a stub is fixed, and a second groove on the second region of the plate and to which a grid holder is fixed, wherein the stub is configured to store test wafer pieces, and wherein the grid holder is configured to store a test sample.

公开(公告)号：US20230067060A1

公开(公告)日：2023-03-02

申请号：US17690317

申请日：2022-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Gon OH ,  Ji Hun KIM ,  Sae Yun KO ,  Gil Ho GU ,  Dong Su KIM ,  Eun Hee LEE ,  Ho Chan LEE ,  Seong Sil JEONG ,  Seong Pyo HONG

IPC: G01R31/28 ,  H01L21/673 ,  H01L21/677

Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.