公开(公告)号：US20240096748A1

公开(公告)日：2024-03-21

申请号：US18453026

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Yongkwan LEE ,  Gyuhyeong KIM ,  Seunghwan KIM ,  Jongwan KIM ,  Junwoo PARK

IPC: H01L23/473 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16052 ,  H01L2224/16175 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/17151 ,  H01L2924/172 ,  H01L2924/177

Abstract: A chip protection device includes a protection frame extending around side surfaces of a semiconductor chip mounted on a substrate. The protection frame includes a plurality of side walls, each wall facing and spaced apart from a respective side surface of the semiconductor chip, and a plurality of upper walls, each upper wall extending inward from an upper portion of a respective side wall toward the semiconductor chip. A plurality of apertures are formed through the side walls and through which a fluid enters and exits. The protection frame defines an inner space in which the fluid can flow via the plurality of apertures. Heat from the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.

公开(公告)号：US20240079342A1

公开(公告)日：2024-03-07

申请号：US18195429

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Junwoo PARK ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package including: a first substrate; a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and a molding layer on the first substrate, the first semiconductor chip and the second substrate, wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate, wherein the molding layer exposes a top surface of the second substrate, and wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.

公开(公告)号：US20230170310A1

公开(公告)日：2023-06-01

申请号：US18103584

申请日：2023-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwan KIM ,  Kyong Hwan KOH ,  Juhyeon OH ,  Yongkwan LEE

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L21/568 ,  H01L23/49816 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.

公开(公告)号：US20240420972A1

公开(公告)日：2024-12-19

申请号：US18402567

申请日：2024-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Yongkwan LEE ,  Gyuhyeong KIM ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK

IPC: H01L21/67 ,  H01L21/56

Abstract: Disclosed are semiconductor molding apparatuses and compression molding methods. The semiconductor molding apparatus comprises an upper mold capable of supporting a substrate, a lower mold that provides a first cavity capable of being filled with a resin, a guide member that provides a second cavity to be filled with the resin and vertically penetrates the lower mold, and a guide lift capable of driving the guide member to vertically move. The lower mold includes a base plate that extends in a horizontal direction and a sidewall member that upwardly extends from the base plate. The guide lift drives the guide member to vertically move such that a top surface of the guide member moves between a top surface of the base plate and a top surface of the sidewall member.

公开(公告)号：US20230127641A1

公开(公告)日：2023-04-27

申请号：US17862662

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan KIM ,  Kyonghwan KOH ,  Jungjoo KIM ,  Jongwan KIM ,  Junwoo PARK ,  Hyunggil BAEK ,  Yongkwan LEE ,  Dongju JANG ,  Taejun JEON

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

公开(公告)号：US20230395482A1

公开(公告)日：2023-12-07

申请号：US18060812

申请日：2022-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungjoo KIM ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK ,  Taejun JEON ,  Junhyeung JO

IPC: H01L23/498 ,  H01L25/16 ,  H01G4/228 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L25/16 ,  H01L25/162 ,  H01G4/228 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01G4/08

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

公开(公告)号：US20160077347A1

公开(公告)日：2016-03-17

申请号：US14838710

申请日：2015-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inkyeong YOO ,  Jungwoo KIM ,  Byeonghak KANG ,  Kwonyoung KIM ,  Jongwan KIM

IPC: G02B27/14 ,  G02B1/14 ,  G06F3/041 ,  G02B1/00

CPC classification number: G06F3/0412 ,  G02B1/005 ,  G02B1/14 ,  G02B5/201 ,  G02B5/26 ,  G06F3/041

Abstract: A film for writing may include: a rough layer, including a non-flat surface, configured to transmit a first light beam and a second light beam of different wavelength bands; and/or a photonic crystal layer, arranged on the rough layer, configured to transmit the first light beam and configured to reflect the second light beam. A film for writing, which transmits visible rays, may include: a non-flat layer. A difference between a maximum thickness and a minimum thickness of the non-flat layer may be from about 220 nanometers (nm) to about 2 microns (μm). A film for writing may include: a first layer; and/or a second layer on the first layer. The first layer may be configured to transmit first and second light beams of different frequency bands. The second layer may be configured to transmit the first light beam, but to reflect the second light beam.

Abstract translation: 用于写入的胶片可以包括：构造成透射不同波长带的第一光束和第二光束的包括非平坦表面的粗糙层; 和/或光子晶体层，被布置在所述粗糙层上，被配置为透射所述第一光束并且被配置为反射所述第二光束。 用于书写的透射可见光线的胶片可以包括：非平坦层。 非平坦层的最大厚度和最小厚度之间的差可以为约220纳米（nm）至约2微米（μm）。 一部写作电影可能包括：第一层; 和/或第一层上的第二层。 第一层可以被配置为透射不同频带的第一和第二光束。 第二层可以被配置为透射第一光束，而是反射第二光束。

公开(公告)号：US20220068835A1

公开(公告)日：2022-03-03

申请号：US17212035

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwan KIM ,  Kyong Hwan KOH ,  Juhyeon OH ,  Yongkwan LEE

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.