TRANSMITTER, WIRELESS COMMUNICATION MODULE AND POWER AMPLIFICATION SYSTEM

    公开(公告)号:US20250070729A1

    公开(公告)日:2025-02-27

    申请号:US18780949

    申请日:2024-07-23

    Abstract: Disclosed is a transmitter. The transmitter includes a plurality of power amplifiers, each of the plurality of power amplifiers being configured to receive an RF input signal, a parallel power combiner configured to combine outputs of the plurality of power amplifiers to generate an RF output signal, a supply voltage switch configured to provide one supply voltage to the plurality of power amplifiers, the one supply voltage being selected from among a plurality of supply voltages of different voltage levels, and a controller configured to control an output power of the RF output signal by selecting the one supply voltage from among the plurality of supply voltages, and controlling whether to activate each of the plurality of power amplifiers.

    METHOD OF IP2 CALIBRATION FOR WIRELESS TRANSCEIVER AND DEVICE FOR PERFORMING IP2 CALIBRATION

    公开(公告)号:US20250167973A1

    公开(公告)日:2025-05-22

    申请号:US18927234

    申请日:2024-10-25

    Abstract: A device configured to perform second order intercept point (IP2) calibration for a wireless transceiver includes a memory storing instructions, an interface, and at least one processor communicatively coupled to the interface and to the memory. The interface is configured to receive, from the wireless transceiver, a signal including second order intermodulation distortion (IMD2), and transmit, to the wireless transceiver, an in-phase correction code (I-correction code) and a quadrature-phase correction code (Q-correction code). The at least one processor is configured to execute the instructions to analyze a level of the IMD2 based on a plurality of heterogeneous methods, and adjust at least one of the I-correction code or the Q-correction code based on analysis results.

    TRANSMITTER AND RECEIVER FOR LOW POWER INPUT/OUTPUT AND MEMORY SYSTEM INCLUDING THE SAME

    公开(公告)号:US20220069822A1

    公开(公告)日:2022-03-03

    申请号:US17353917

    申请日:2021-06-22

    Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

Patent Agency Ranking