公开(公告)号：US10296065B2

公开(公告)日：2019-05-21

申请号：US15414969

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F13/42 ,  G06F1/06 ,  H04J3/06 ,  H04J3/14 ,  H04L12/933

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

公开(公告)号：US11625606B2

公开(公告)日：2023-04-11

申请号：US17895190

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Ook Song ,  Jun Seok Park ,  Yun Kyo Cho

IPC: G06N3/08 ,  G06N3/04 ,  G06F1/26 ,  G06F1/06

Abstract: A neural processing system includes a first frontend module, a second frontend module, a first backend module, and a second backend module. The first frontend module executes a feature extraction operation using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second frontend module executes the feature extraction operation using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first backend module receives an input of the first operation result provided from the first frontend module and the fourth operation result provided from the second frontend module via a second bridge to sum up the first operation result and the fourth operation result. The second backend module receives an input of the third operation result provided from the second frontend module and the second operation result provided from the first frontend module via a first bridge to sum up the third operation result and the second operation result.

公开(公告)号：US11443183B2

公开(公告)日：2022-09-13

申请号：US16507995

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Ook Song ,  Jun Seok Park ,  Yun Kyo Cho

IPC: G06N3/08 ,  G06N3/04 ,  G06F1/26 ,  G06F1/06

Abstract: A neural processing system includes a first frontend module, a second frontend module, a first backend module, and a second backend module. The first frontend module executes a feature extraction operation using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second frontend module executes the feature extraction operation using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first backend module receives an input of the first operation result provided from the first frontend module and the fourth operation result provided from the second frontend module via a second bridge to sum up the first operation result and the fourth operation result. The second backend module receives an input of the third operation result provided from the second frontend module and the second operation result provided from the first frontend module via a first bridge to sum up the third operation result and the second operation result.

公开(公告)号：US10969854B2

公开(公告)日：2021-04-06

申请号：US16416600

申请日：2019-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/06 ,  G06F13/42 ,  H04J3/06 ,  H04J3/14 ,  H04L12/933 ,  G06F1/20 ,  G06F1/3237 ,  G06F1/10

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

公开(公告)号：US11789515B2

公开(公告)日：2023-10-17

申请号：US17731953

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/06 ,  G06F13/42 ,  H04J3/06 ,  H04J3/14 ,  H04L49/109 ,  G06F1/20 ,  G06F1/3237 ,  G06F1/10

CPC classification number: G06F1/3234 ,  G06F1/06 ,  G06F1/10 ,  G06F1/206 ,  G06F1/3237 ,  G06F1/3243 ,  G06F13/42 ,  H04J3/0658 ,  H04J3/14 ,  H04L49/109 ,  Y02D10/00

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

公开(公告)号：US11340685B2

公开(公告)日：2022-05-24

申请号：US17159318

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/06 ,  G06F13/42 ,  H04J3/06 ,  H04J3/14 ,  H04L49/109 ,  G06F1/20 ,  G06F1/3237 ,  G06F1/10

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

公开(公告)号：US10432183B2

公开(公告)日：2019-10-01

申请号：US16388602

申请日：2019-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Ook Song ,  Bong Il Park ,  Jae Gon Lee

IPC: H03K5/135 ,  H03K5/05 ,  H03K5/00 ,  H03K19/20

Abstract: A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.

公开(公告)号：US09985610B2

公开(公告)日：2018-05-29

申请号：US15414787

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Woo Kim ,  Suk Nam Kwon ,  Jin Ook Song

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/012

Abstract: A semiconductor device includes a power gating circuit including a synchronous reset flip-flop, a retention circuit including a retention flip-flop, a clock management circuit configured to provide an operation clock to the power gating circuit and the retention circuit, and a power management circuit configured to transmit a power gating control signal to the power gating circuit, the retention circuit, and the clock management circuit. The power gating circuit is activated to signal entry to a power reduction mode. The retention circuit retains states of the semiconductor device. Upon exit from the power reduction mode, the power management circuit is configured to complete a reset operation of the power gating circuit before signaling the retention circuit to cancel a retention state and restore the states of the semiconductor device.