公开(公告)号：US12205914B2

公开(公告)日：2025-01-21

申请号：US17648425

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung Song ,  Seokhyun Lee ,  Jongyoun Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.

公开(公告)号：US20240136250A1

公开(公告)日：2024-04-25

申请号：US18197998

申请日：2023-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Inhyung Song ,  Kyungdon Mun ,  Hyeonjeong Hwang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/3738 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/165 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.

公开(公告)号：US20240065002A1

公开(公告)日：2024-02-22

申请号：US18231341

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Joonsung Kim ,  Inhyung Song ,  Yeonho Jang

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/96 ,  H01L2224/214 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L24/32 ,  H01L2224/32145 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/17181 ,  H01L24/16 ,  H01L24/17 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/16145

Abstract: A semiconductor device including a first lower buffer chip, an upper buffer chip disposed on an upper surface of the first lower buffer chip, a plurality of conductive posts spaced apart from the first lower buffer chip and disposed on a lower surface of the upper buffer chip, and a first memory chip stack structure disposed on the upper buffer chip and including a plurality of first memory chips.

公开(公告)号：US11887931B2

公开(公告)日：2024-01-30

申请号：US17213506

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung Song ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Wonkyoung Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L27/08 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.