公开(公告)号：US11887931B2

公开(公告)日：2024-01-30

申请号：US17213506

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung Song ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Wonkyoung Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L27/08 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US11942458B2

公开(公告)日：2024-03-26

申请号：US17511178

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohwan Lee ,  Wonkyoung Choi ,  Jeongho Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L25/105 ,  H01L21/56 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/20 ,  H01L24/73 ,  H01L25/0652 ,  H01L24/48 ,  H01L2224/023 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/48225 ,  H01L2224/73209 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/181

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

公开(公告)号：US20240040806A1

公开(公告)日：2024-02-01

申请号：US18125928

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Jihwang Kim ,  Jeongho Lee ,  Dongwook Kim ,  Wonkyoung Choi ,  Yunseok Choi

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L23/36 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253

Abstract: A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.