公开(公告)号：US20160148808A1

公开(公告)日：2016-05-26

申请号：US14554107

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyuk KIM ,  Kang-III SEO ,  Hyun-Jae KANG ,  Deok-Han BAE

IPC: H01L21/033 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成多个目标图案。 多个目标图案沿着第一方向彼此平行地延伸。 形成在第一方向上延伸并且包括多个第一开口的第一掩模图案。 形成沿与第一方向交叉的第二方向延伸并且包括多个第二开口的第二掩模图案。 每个第二开口与每个第一开口重叠以形成重叠的开口区域。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，通过重叠的开口区域蚀刻多个目标图案的区域。 多个目标图案的区域与重叠的开口区域重叠。

公开(公告)号：US20160049394A1

公开(公告)日：2016-02-18

申请号：US14629249

申请日：2015-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon-Jong SHIN ,  Deok-Han BAE ,  Dae-Hee WEON ,  Hwi-Chan JUN

IPC: H01L27/088 ,  H01L29/417 ,  H01L23/532 ,  H01L29/45 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/76804 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a transistor formed on a substrate and including a gate electrode and a source/drain, an interlayer insulating layer covering the transistor, a first contact hole formed in the interlayer insulating layer to expose a part of the transistor, a first barrier metal conformally formed on an inner surface of the first contact hole, a first conductive layer formed on the first barrier metal to fill the first contact hole, a second contact hole formed on the first conductive layer in the interlayer insulating layer and having a larger width than the first contact hole, a second barrier metal conformally formed on an inner surface of the second contact hole, and a second conductive layer formed on the second barrier metal to fill the second contact hole, wherein the second barrier metal is formed between the first conductive layer and the second conductive layer.

Abstract translation: 半导体器件包括形成在衬底上并包括栅极和源极/漏极的晶体管，覆盖晶体管的层间绝缘层，形成在层间绝缘层中以暴露晶体管的一部分的第一接触孔，第一栅极 在第一接触孔的内表面上保形地形成的金属，形成在第一阻挡金属上以填充第一接触孔的第一导电层，形成在层间绝缘层中的第一导电层上并具有较大宽度的第二接触孔 形成在第二接触孔的内表面上的第二阻挡金属和形成在第二阻挡金属上以填充第二接触孔的第二导电层，其中第二阻挡金属形成在第一接触孔之间， 导电层和第二导电层。

公开(公告)号：US20160020303A1

公开(公告)日：2016-01-21

申请号：US14670324

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi-Chan JUN ,  Deok-Han BAE ,  Hyun-Seung SONG ,  Seung-Seok HA

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656

Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

Abstract translation: 本公开的实施例涉及一种用于制造包括具有改善的电特性的场效应晶体管的半导体器件的方法。 根据本公开的实施例，可以使用设置在栅极部分上的金属硬掩模部分来有效地形成自对准接触插塞。 此外，通过使用金属硬掩模部分，可以提高用于形成自对准接触插塞的光刻胶掩模的工艺余量。