公开(公告)号：US11652076B2

公开(公告)日：2023-05-16

申请号：US17736536

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeho Ko ,  Daehee Lee ,  Hyunchul Jung

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/24 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/03462 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/245 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/82101 ,  H01L2224/82106

Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

公开(公告)号：US20240297275A1

公开(公告)日：2024-09-05

申请号：US18545667

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungjun KOH ,  Daehee Lee ,  Yeseul Park ,  Yongdok Cha

IPC: H01L33/50 ,  H01L25/075 ,  H01L33/58

CPC classification number: H01L33/502 ,  H01L25/0753 ,  H01L33/58

Abstract: A display apparatus includes a display module array including a plurality of display modules that are horizontally arranged in a form of a matrix. Each display module includes a substrate including a mounting surface and a rear surface opposite to the mounting surface; a metal plate bonded to the rear surface and configured to dissipate heat from the substrate; a front cover covering the mounting surface; inorganic light emitting devices electrically connected to the mounting surface; and a color layer between the inorganic light emitting devices and the front cover. The color layer includes a scattering layer through which light emitted from a third inorganic light emitting device passes. Each display module further includes scattering particles provided in the scattering layer and configured to scatter the light emitted from the third inorganic light emitting device and passing through the scattering layer.

公开(公告)号：US11355467B2

公开(公告)日：2022-06-07

申请号：US16983296

申请日：2020-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeho Ko ,  Daehee Lee ,  Hyunchul Jung

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

公开(公告)号：US12255140B2

公开(公告)日：2025-03-18

申请号：US17867195

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungil Chai ,  Kyunghee Shin ,  Daehee Lee ,  Moonhui Lee

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/35

Abstract: A semiconductor device, includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and a plurality of interconnection patterns connected to the plurality of semiconductor elements, wherein the plurality of interconnection patterns include a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction, a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and a routing interconnection adjacent to at least one of the plurality of semiconductor elements in the second direction, wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second direction.