公开(公告)号：US09698158B2

公开(公告)日：2017-07-04

申请号：US15248564

申请日：2016-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Seok Jung ,  Changseok Kang ,  Seungwoo Paek ,  Inseok Yang ,  Kyungjoong Joo

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

公开(公告)号：US20190312052A1

公开(公告)日：2019-10-10

申请号：US16232549

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  Changseok Kang ,  Yongseok Kim ,  Junhee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.

公开(公告)号：US09484355B2

公开(公告)日：2016-11-01

申请号：US14801470

申请日：2015-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Seok Jung ,  Changseok Kang ,  SeungWoo Paek ,  Inseok Yang ,  Kyungjoong Joo

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

Abstract translation: 半导体器件包括衬底，堆叠结构，外围栅极结构和残余间隔物。 衬底包括电池阵列区域和外围电路区域。 堆叠结构设置在电池阵列区域上，具有交替堆叠的电极和绝缘层。 外围栅极结构设置在外围电路区域上，在一个方向上彼此间隔开并且具有设置在基板上的周边栅极图案，以及设置在外围栅极图案的侧壁上的外围栅极间隔件。 剩余间隔物设置在外围栅极结构的侧壁上，具有堆叠的牺牲图案和绝缘图案。 绝缘图案包括与堆叠结构的绝缘层基本相同的材料。

公开(公告)号：US10818689B2

公开(公告)日：2020-10-27

申请号：US16232549

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Changseok Kang ,  Yongseok Kim ,  Junhee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/311 ,  H01L27/11573 ,  H01L21/28

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.

公开(公告)号：US09991275B2

公开(公告)日：2018-06-05

申请号：US15057412

申请日：2016-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Changseok Kang ,  Byeong-In Choe

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.

公开(公告)号：US09466704B2

公开(公告)日：2016-10-11

申请号：US14291099

申请日：2014-05-30

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Sung-il Chang ,  Changseok Kang ,  Jungdal Choi

IPC: H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/51 ,  G11C16/10 ,  G11C16/14

CPC classification number: H01L29/66833 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/513 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved.

Abstract translation: 提供一种非易失性存储器件及其制造方法。 在非易失性存储器件中，在阱绝缘层和栅电极之间设置阻挡绝缘层。 在隔离绝缘层中设置有与栅电极间隔开的固定电荷层。 因此，提高了非易失性存储装置的可靠性。