Abstract:
An image processing apparatus includes a camera configured to generate first image data, a pre-processor configured to generate second image data based on performing a pre-processing operation on the first image data, a neural network processor configured to generate third image data based on performing an image processing operation on the second image data based on using a neural network model trained to perform one or more particular image processing operations, and a main processor configured to generate corrected image data based on performing a post-processing operation on the third image data.
Abstract:
An electronic device may include a first defective pixel corrector configured to correct pixel values of defective pixels among the plurality of pixels by using pixel values of neighboring pixels of each of the defective pixels and generate first pixel data, the pixel values of the defective pixels being included in the image data, and a second defective pixel corrector configured to correct a pixel value of a cluster of defective pixels by using a neural network and generate second pixel data, the pixel value of the cluster of defective pixels being included in the image data, and the neural network being trained to correct the cluster of defective pixels.
Abstract:
An image sensor includes: a pixel array including a plurality of sensing pixels each configured to convert a received light signal into an electrical signal; a readout circuit configured to convert the electrical signals into image data and output the image data; and a bad pixel correction circuit configured to: input, to a neural network, first input data comprising a first cluster bad pixel of the image data in a first direction to generate a first corrected pixel data, and flip second input data comprising a second cluster bad pixel of the image data in a second direction to generate third input data, and input, to the neural network, the third input data to generate a second corrected pixel data.
Abstract:
A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page.
Abstract:
An image processing apparatus includes a pre-processor configured to receive, from an image sensor, input image data including a pattern corresponding to a filter array of the image sensor, and generate reconstructed image data by reconstructing the input image data based on phase information corresponding to each of a plurality of pixels of the image sensor, and a neural network processor configured to generate output image data based on the input image data and the reconstructed image data.
Abstract:
A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.
Abstract:
A memory system comprises a nonvolatile memory comprising a memory block having multiple pages, and a controller configured to control the nonvolatile memory to store data in the memory block according to a command and logical address received from an external source. The controller is configured to determine whether the logical address is currently mapped to a bad page of the memory block by referring to a bad page map, and as a consequence of determining that the logical address corresponds to the bad page, remaps the logical address to a different page and stores dummy data in the bad page.