公开(公告)号：US20150357349A1

公开(公告)日：2015-12-10

申请号：US14828384

申请日：2015-08-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Yang Ho BAE ,  Beom-Seok CHO ,  Chang Oh JEONG

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US20140061631A1

公开(公告)日：2014-03-06

申请号：US13826905

申请日：2013-03-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Jin Hun LIM ,  Jun Ho SONG

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78696

Abstract: A thin film transistor and a manufacturing method thereof. The thin film transistor includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first semiconductor disposed on the gate insulating layer; a second semiconductor disposed on the first semiconductor and having a different plane shape from the first semiconductor; and a source electrode and a drain electrode that are disposed on the second semiconductor and face each other.

Abstract translation: 一种薄膜晶体管及其制造方法。 薄膜晶体管包括：栅电极; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的第一半导体; 设置在所述第一半导体上并且具有与所述第一半导体不同的平面形状的第二半导体; 以及设置在第二半导体上并且彼此面对的源电极和漏电极。

公开(公告)号：US20160172508A1

公开(公告)日：2016-06-16

申请号：US14701325

申请日：2015-04-30

Applicant: Samsung Display Co. Ltd.

Inventor： Je Hun LEE ,  Byung Hwan CHU

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/1237 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: A thin film transistor having uniform electrical characteristics and reduced power consumption is presented. The thin film transistor includes a semiconductor layer, a first metal oxide layer coming in contact with the semiconductor layer and having thermal conductivity that is lower than the thermal conductivity of the semiconductor layer and a second metal oxide layer coming in contact with the first metal oxide layer and having thermal conductivity that is higher than the thermal conductivity of the first metal oxide layer.

Abstract translation: 介绍了具有均匀电特性和降低功耗的薄膜晶体管。 薄膜晶体管包括半导体层，与半导体层接触并具有低于半导体层的热导率的热导率的第一金属氧化物层和与第一金属氧化物接触的第二金属氧化物层 并且具有比第一金属氧化物层的热导率高的导热性。

公开(公告)号：US20150333184A1

公开(公告)日：2015-11-19

申请号：US14809830

申请日：2015-07-27

Applicant: Samsung Display Co., Ltd.

Inventor： Je Hun LEE ,  Jun Ho SONG ,  Yun Jong YEO ,  Hwa Dong JUNG

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

Abstract: The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

公开(公告)号：US20150333154A1

公开(公告)日：2015-11-19

申请号：US14808769

申请日：2015-07-24

Applicant: Samsung Display Co., Ltd.

Inventor： Je Hun LEE ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

IPC: H01L29/66 ,  H01L29/40 ,  H01L27/12 ,  H01L21/268 ,  H01L21/308 ,  H01L21/02 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

Abstract: The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

Abstract translation: 本发明涉及薄膜晶体管，薄膜晶体管阵列面板及其制造方法。 根据本发明的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 与所述栅电极重叠的沟道区，位于所述沟道区与所述栅电极之间的所述栅绝缘层; 以及源极区域和漏极区域，其相对于沟道区域彼此面对，位于与沟道区域相同的层中，并且连接到沟道区域，其中沟道区域，源极区域和漏极区域包括 氧化物半导体，其中源极区域和漏极区域的载流子浓度大于沟道区域的载流子浓度。

公开(公告)号：US20150171226A1

公开(公告)日：2015-06-18

申请号：US14635732

申请日：2015-03-02

Applicant: Samsung Display Co., Ltd. ,  Kookmin University Industry Academy Cooperation Foundation

Inventor： Byung Du AHN ,  Ji Hun LIM ,  Jun Hyung LIM ,  Dae Hwan KIM ,  Jae Hyeong KIM ,  Je Hun LEE ,  Hyun Kwang JUNG

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。

公开(公告)号：US20170053800A1

公开(公告)日：2017-02-23

申请号：US15290715

申请日：2016-10-11

Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.) ,  Samsung Display Co. , Ltd.

Inventor： Hiroaki TAO ,  Aya MIKI ,  Shinya MORITA ,  Satoshi YASUNO ,  Toshihiro KUGIMIYA ,  Jae Woo PARK ,  Je Hun LEE ,  Byung Du AHN ,  Gun Hee KIM

IPC: H01L21/02 ,  H01L21/477

CPC classification number: H01L21/02554 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02587 ,  H01L21/02631 ,  H01L21/477 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7869

Abstract: The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≦0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])>0.5. [In]/([In]+[Zn]+[Sn])≦0.3 - - - (1), [In]/([In]+[Zn]+[Sn])≦1.4×{[Zn]/([Zn]+[Sn])}−0.5 - - - (2), [Zn]/([In]+[Zn]+[Sn])≦0.83 - - - (3), and 0.1≦[In]/([In]+[Zn]+[Sn]) - - - (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

Abstract translation: 用于薄膜晶体管的本发明的氧化物是含有In，Zn和Sn的In-Zn-Sn系氧化物，其中，当In-Zn-Sn系中含有的金属元素的含量（原子％ 当[In] /（[In] + [Sn]）[Zn]，[In] + [Sn]表示[Zn]，[Sn]和[In]时，In-Zn-Sn系氧化物满足下述（2） ]）≤0.5; 当[In] /（[In] + [Sn]）> 0.5时，或以下表达式（1），（3）和（4）。 [In] /（[In] + [Zn] + [Sn]）≤0.3 - - - （1），[In] /（[In] + [Zn] + [Sn]）≤1.4×{[Zn] /([Zn]+[Sn])}-0.5 - - - （2），[Zn] /（[In] + [Zn] + [Sn]）≤0.83 - - - （3）和0.1≤[ In] /（[In] + [Zn] + [Sn]） - - - （4）。 根据本发明，可以获得用于薄膜晶体管的氧化物薄膜，其提供具有优异的开关特性的TFT，并且在溅射中具有高溅射速率并且在湿蚀刻中具有适当控制的蚀刻速率。

公开(公告)号：US20140103332A1

公开(公告)日：2014-04-17

申请号：US13789335

申请日：2013-03-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Ji Hun LIM ,  Jun Hyung LIM ,  Dae Hwan KIM ,  Jae Hyeong KIM ,  Je Hun LEE ,  Hyun Kwang JUNG

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。

公开(公告)号：US20130056740A1

公开(公告)日：2013-03-07

申请号：US13669278

申请日：2012-11-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Yang Ho BAE ,  Beom-Seok CHO ,  Chang Oh JEONG

IPC: H01L33/08

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

公开(公告)号：US20140167054A1

公开(公告)日：2014-06-19

申请号：US14165399

申请日：2014-01-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Yang Ho BAE ,  Beom-Seok CHO ,  Chang Oh JEONG

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。