公开(公告)号：US07793170B2

公开(公告)日：2010-09-07

申请号：US11028900

申请日：2005-01-03

Applicant: Roshan Rajendra Baliga ,  Rahul Garg ,  Rajendra Kumar ,  Sreenath Ramanath

Inventor： Roshan Rajendra Baliga ,  Rahul Garg ,  Rajendra Kumar ,  Sreenath Ramanath

IPC: G11C29/00

CPC classification number: H04L27/265 ,  H03M13/2792 ,  H04L1/0071 ,  H04L27/263

Abstract: A novel technique for combining deinterleaving operation with Fast Fourier Transformer (FFT) modules and other post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with FFT and demapper operations to reduce the processing time and complexity.

Abstract translation: 一种用于将解交织操作与快速傅里叶变换器（FFT）模块和其他后FFT模块组合在接收器中以减少处理时间的新颖技术。 在一个示例实施例中，后FFT模块中的去交织操作与FFT和解映射器操作组合以减少处理时间和复杂性。

公开(公告)号：US07388881B2

公开(公告)日：2008-06-17

申请号：US11067968

申请日：2005-02-28

Applicant: Roshan Rajendra Baliga ,  Rahul Garg ,  Rajendra Kumar

Inventor： Roshan Rajendra Baliga ,  Rahul Garg ,  Rajendra Kumar

IPC: H04J3/22

CPC classification number: H04L7/10 ,  H04B1/7073

Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 uS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.

Abstract translation: 用于接收和处理包括具有帧定界符（SFD）开始的前同步码的加扰输入数据信号的系统启动对加扰输入数据的SFD搜索，从而尝试保存初始化周期。 初始化时间可以是7μS的量级，并且其保存导致改进的时间线管理，使天线分集和可能使用高性能算法。 系统可以使用两个并行路径进行信号处理，每个路径都有一个SFD检测器和一个解扰器。 如果检测到的SFD短，则禁用第二条路径，如果长度不等，则第一条并行路径被禁用。 或者，第一路径可以用于有限的时间段（例如，40个符号），并且如果尚未检测到SFD，则禁用第一路径，并且系统仅使用第二路径。

公开(公告)号：US20050257112A1

公开(公告)日：2005-11-17

申请号：US11028900

申请日：2005-01-03

Applicant: Roshan Baliga ,  Rahul Garg ,  Rajendra Kumar ,  Sreenath Ramanath

Inventor： Roshan Baliga ,  Rahul Garg ,  Rajendra Kumar ,  Sreenath Ramanath

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  G11C29/00 ,  H03M13/00 ,  H03M13/27 ,  H04L1/00 ,  H04L27/26

CPC classification number: H04L27/265 ,  H03M13/2792 ,  H04L1/0071 ,  H04L27/263

Abstract: A novel technique for combining deinterleaving operation with post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with FFT and demapper operations to reduce the processing time and complexity.

Abstract translation: 一种用于将解交织操作与接收机中的后FFT模块组合以减少处理时间的新颖技术。 在一个示例实施例中，后FFT模块中的去交织操作与FFT和解映射器操作组合以减少处理时间和复杂性。

公开(公告)号：US20050195770A1

公开(公告)日：2005-09-08

申请号：US11067968

申请日：2005-02-28

Applicant: Roshan Baliga ,  Rahul Garg ,  Rajendra Kumar

Inventor： Roshan Baliga ,  Rahul Garg ,  Rajendra Kumar

IPC: H04B1/69 ,  H04B7/216

CPC classification number: H04L7/10 ,  H04B1/7073

Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 μS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.

Abstract translation: 用于接收和处理包括具有帧定界符（SFD）开始的前同步码的加扰输入数据信号的系统启动对加扰输入数据的SFD搜索，从而尝试保存初始化周期。 初始化时间可以是7μs的量级，并且其节省结果是改善了时间线管理，从而实现了天线分集和可能使用高性能算法。 系统可以使用两个并行路径进行信号处理，每个路径都有一个SFD检测器和一个解扰器。 如果检测到的SFD短，则禁用第二条路径，如果长度不等，则第一条并行路径被禁用。 或者，第一路径可以用于有限的时间段（例如，40个符号），并且如果尚未检测到SFD，则禁用第一路径，并且系统仅使用第二路径。

公开(公告)号：US07974181B2

公开(公告)日：2011-07-05

申请号：US12138731

申请日：2008-06-13

Applicant: Amitkumar Mahadevan ,  Patrick Duvaut ,  Harish Jethanandani ,  Rahul Garg

Inventor： Amitkumar Mahadevan ,  Patrick Duvaut ,  Harish Jethanandani ,  Rahul Garg

IPC: H04J11/00

CPC classification number: H04L27/2618

Abstract: Systems and methods for reducing the peak-to-average power ratio (PAR) at the transmitter can reduce the dynamic range required in various analog components. PAR can be reduced by applying a time-domain compensation signal in the oversampled regime, using tones reserved for PAR reduction. A set of vectors corresponding to PAR tones is generated by processing out-of-phase symbols for each PAR tone to form a span matrix. The span matrix is used to find a best fit of a desired target signal to a time-domain compensation signal comprising only PAR tones.

Abstract translation: 用于降低发射机的峰均功率比（PAR）的系统和方法可以减少各种模拟组件所需的动态范围。 可以通过在过采样方案中应用时域补偿信号，使用保留给PAR减少的音调来减少PAR。 通过处理每个PAR色调的异相符号来生成对应于PAR色调的一组矢量以形成跨度矩阵。 跨度矩阵用于找到期望目标信号对仅包括PAR色调的时域补偿信号的最佳拟合。

公开(公告)号：US20100061437A1

公开(公告)日：2010-03-11

申请号：US12348565

申请日：2009-01-05

Applicant: Hemant Samdani ,  Kunal Raheja ,  Rahul Garg ,  Amitkumar Mahadevan ,  Patrick Duvaut

Inventor： Hemant Samdani ,  Kunal Raheja ,  Rahul Garg ,  Amitkumar Mahadevan ,  Patrick Duvaut

IPC: H04B17/00

CPC classification number: H04B3/46

Abstract: Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines (DSL). The characterization of the nature, timing and length of impulse noise sources present on a DSL loop is a critical first step in mitigating the effect of impulse noise on DSL communications. DSL standards provide histograms for impulse length and inter-arrival time of impulses. These histograms can be used to derive the nature, maximum frequency and other statistics related to impulse noise on a DSL line.

Abstract translation: 来自附近或强电场的脉冲噪声可能会扰乱通过数字用户线路（DSL）的通信。 存在于DSL环路上的脉冲噪声源的性质，时间和长度的表征是减轻脉冲噪声对DSL通信的影响的关键的第一步。 DSL标准提供脉冲长度和脉冲到达间隔时间的直方图。 这些直方图可用于导出与DSL线路上的脉冲噪声有关的性质，最大频率和其他统计。

公开(公告)号：US07613981B2

公开(公告)日：2009-11-03

申请号：US11851383

申请日：2007-09-06

Applicant: Rahul Garg ,  Amrit Singh

Inventor： Rahul Garg ,  Amrit Singh

IPC: H03M13/00

CPC classification number: H03M13/114 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/3738 ,  H03M13/3753 ,  H03M13/6502 ,  H03M13/6527 ,  H03M13/6544

Abstract: A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

Abstract translation: 用于降低低密度奇偶校验码（LDPC）解码器中的功耗的系统和方法包括睡眠模式检查模块和门控电路。 睡眠模式检查模块检查校验节点是否处于睡眠模式。 当到达对应于校验节点的一个或多个比特节点中的每一个的消息的绝对值大于阈值时，该校验节点被认为处于睡眠模式。 当校验节点处于睡眠模式时，门控电路关闭与校验节点相关联的校验节点和位节点更新单元（CNBNU）。 关闭CNBNU会停止校验节点与其相应的一个或多个位节点之间的消息交换。

公开(公告)号：US07463681B2

公开(公告)日：2008-12-09

申请号：US11121475

申请日：2005-05-04

Applicant: Rahul Garg ,  Kiran Devanahalli ,  Aparna Chakrakodi Krishnashastry

Inventor： Rahul Garg ,  Kiran Devanahalli ,  Aparna Chakrakodi Krishnashastry

IPC: H03H7/30 ,  H03H7/40

CPC classification number: H04L23/02 ,  H04L25/03057 ,  H04L2025/03566

Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.

Abstract translation: 判决反馈均衡器（DFE）具有符号间干扰（ISI）环路和芯片间干扰（ICI）环路。 DFE循环输入端的一个缓冲器接收到进入DFE的基于（基于CCK的数据速率）信号，从每个输入符号保留预定数量的芯片，并通过芯片管理帮助满足定时要求。 来自缓冲器的芯片的输出速率可以取决于输入速率，并且可以通过已知因素高于输入速率。 设计DFE的配置的方法考虑了循环中的定时延迟。 DFE循环中的操作是流水线的，并且由于流水线的任何延迟在CCK解调器处理。 还公开了一种用于设计DFE架构的方法和包括其上具有用于执行该方法的指令的存储介质的物品。

公开(公告)号：US07269706B2

公开(公告)日：2007-09-11

申请号：US11008525

申请日：2004-12-09

Applicant: Saurabh Agarwal ,  Rahul Garg ,  Meeta S Gupta

Inventor： Saurabh Agarwal ,  Rahul Garg ,  Meeta S Gupta

IPC: G06F12/00

CPC classification number: G06F11/1451

Abstract: A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.

Abstract translation: 公开了一种方法，装置和计算机程序产品，用于在周期性时刻在存在至少一个执行软件应用的情况下递增地检查计算机存储器的状态。 周期性地对每个分区的连续的存储器块应用安全的散列函数以给出周期性的块哈希值。 在每个周期性时刻，将每个块的块哈希值与相应的先前块散列值进行比较，以根据所述块哈希值是否不同来确定所述存储块是否已经改变。 只有更改的内存块才被存储在检查点记录中。 存储器块大小在每个周期性时刻被适配，以将改变的块分成至少两个部分，并且一次仅合并两个未改变的连续块。

公开(公告)号：US06976005B1

公开(公告)日：2005-12-13

申请号：US09667169

申请日：2000-09-21

Applicant: Vipul Bansal ,  Rahul Garg

Inventor： Vipul Bansal ,  Rahul Garg

IPC: G06Q30/06 ,  G06Q30/08 ,  G06F17/60

CPC classification number: G06Q40/04 ,  G06Q30/0617 ,  G06Q30/08

Abstract: The use of software-based agents to act on behalf of human bidders for dynamic participation in multiple simultaneous online auctions is disclosed. The software-based agents may reside on computer systems or on any type of stationary or mobile terminal. On the basis of bidding-related information from a bidder, a software agent selects a plurality of auctions to place bids in. Upon being outbid, the agent determines whether to place an additional bid in a further auction. The agent can make such a determination on the basis of maximising profitability or surplus.

Abstract translation: 公开了使用基于软件的代理人代表人类投标人动态参与多个同时在线拍卖。 基于软件的代理可以驻留在计算机系统或任何类型的固定或移动终端上。 根据投标人的投标相关信息，软件代理人选择多个拍卖进行投标。经过一段时间后，代理商确定是否在进一步的拍卖中再次出价。 代理人可以在最大化盈利能力或盈余的基础上做出这样的决定。