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公开(公告)号：US20050195770A1
公开(公告)日：2005-09-08
申请号：US11067968
申请日：2005-02-28
Applicant: Roshan Baliga , Rahul Garg , Rajendra Kumar
Inventor： Roshan Baliga , Rahul Garg , Rajendra Kumar
CPC classification number: H04L7/10 , H04B1/7073
Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 μS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.
Abstract translation: 用于接收和处理包括具有帧定界符（SFD）开始的前同步码的加扰输入数据信号的系统启动对加扰输入数据的SFD搜索，从而尝试保存初始化周期。 初始化时间可以是7μs的量级，并且其节省结果是改善了时间线管理，从而实现了天线分集和可能使用高性能算法。 系统可以使用两个并行路径进行信号处理，每个路径都有一个SFD检测器和一个解扰器。 如果检测到的SFD短，则禁用第二条路径，如果长度不等，则第一条并行路径被禁用。 或者，第一路径可以用于有限的时间段（例如，40个符号），并且如果尚未检测到SFD，则禁用第一路径，并且系统仅使用第二路径。
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2.发明申请公开(公告)号：US20050257112A1
公开(公告)日：2005-11-17
申请号：US11028900
申请日：2005-01-03
Applicant: Roshan Baliga , Rahul Garg , Rajendra Kumar , Sreenath Ramanath
Inventor： Roshan Baliga , Rahul Garg , Rajendra Kumar , Sreenath Ramanath
CPC classification number: H04L27/265 , H03M13/2792 , H04L1/0071 , H04L27/263
Abstract: A novel technique for combining deinterleaving operation with post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with FFT and demapper operations to reduce the processing time and complexity.
Abstract translation: 一种用于将解交织操作与接收机中的后FFT模块组合以减少处理时间的新颖技术。 在一个示例实施例中，后FFT模块中的去交织操作与FFT和解映射器操作组合以减少处理时间和复杂性。
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3.发明授权公开(公告)号：US07793170B2
公开(公告)日：2010-09-07
申请号：US11028900
申请日：2005-01-03
Applicant: Roshan Rajendra Baliga , Rahul Garg , Rajendra Kumar , Sreenath Ramanath
Inventor： Roshan Rajendra Baliga , Rahul Garg , Rajendra Kumar , Sreenath Ramanath
IPC: G11C29/00
CPC classification number: H04L27/265 , H03M13/2792 , H04L1/0071 , H04L27/263
Abstract: A novel technique for combining deinterleaving operation with Fast Fourier Transformer (FFT) modules and other post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with FFT and demapper operations to reduce the processing time and complexity.
Abstract translation: 一种用于将解交织操作与快速傅里叶变换器（FFT）模块和其他后FFT模块组合在接收器中以减少处理时间的新颖技术。 在一个示例实施例中，后FFT模块中的去交织操作与FFT和解映射器操作组合以减少处理时间和复杂性。
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公开(公告)号：US07388881B2
公开(公告)日：2008-06-17
申请号：US11067968
申请日：2005-02-28
Applicant: Roshan Rajendra Baliga , Rahul Garg , Rajendra Kumar
Inventor： Roshan Rajendra Baliga , Rahul Garg , Rajendra Kumar
IPC: H04J3/22
CPC classification number: H04L7/10 , H04B1/7073
Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 uS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.
Abstract translation: 用于接收和处理包括具有帧定界符（SFD）开始的前同步码的加扰输入数据信号的系统启动对加扰输入数据的SFD搜索，从而尝试保存初始化周期。 初始化时间可以是7μS的量级，并且其保存导致改进的时间线管理，使天线分集和可能使用高性能算法。 系统可以使用两个并行路径进行信号处理，每个路径都有一个SFD检测器和一个解扰器。 如果检测到的SFD短，则禁用第二条路径，如果长度不等，则第一条并行路径被禁用。 或者，第一路径可以用于有限的时间段（例如，40个符号），并且如果尚未检测到SFD，则禁用第一路径，并且系统仅使用第二路径。
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公开(公告)号：US09071494B2
公开(公告)日：2015-06-30
申请号：US13486608
申请日：2012-06-01
Applicant: Rajendra Kumar
Inventor： Rajendra Kumar
CPC classification number: H04L27/2657 , H03H21/003 , H04L27/20 , H04L27/2676 , H04L27/2688
Abstract: Systems and methods are provided for fast and precise estimation of frequency with relatively minimal sampling and relatively high tolerance to noise.
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Patent Agency Ranking
6.发明授权Multi transform OFDM systems and methods with low peak to average power ratio signals 有权具有低峰值与平均功率比信号的多变换OFDM系统和方法公开(公告)号：US08995542B2
公开(公告)日：2015-03-31
申请号：US13913761
申请日：2013-06-10
Applicant: Rajendra Kumar
Inventor： Rajendra Kumar
CPC classification number: H04L27/2602 , H04L27/2614 , H04L27/2615 , H04L27/2618
Abstract: Various embodiments of the invention are directed to methods and systems for multi transform OFDM transmitter and receivers with low peak to average power ratio (PAPR) signals, that have high bandwidth efficiency and are computational efficient. For example, various embodiments of the transmitter may utilize an architecture comprised of a baseband modulator, a serial to parallel converter, a bank of multiplicity NT orthonormal transforms unit, a bank of multiplicity NT inverse Fourier transforms unit, a dummy symbols generator, and a minimum PAPR evaluation unit for finding the optimum transform index n0. Various embodiments of the receiver may comprise of a transform index detection unit for the detection of the transform index imbedded in the OFDM signal.
Abstract translation: 本发明的各种实施例涉及具有低峰值与平均功率比（PAPR）信号的具有高带宽效率并且具有计算效率的多变换OFDM发射机和接收机的方法和系统。 例如，发射机的各种实施例可以利用包括基带调制器，串行到并行转换器，多重组NT正交变换单元组，多重组NT逆傅里叶变换单元组，虚拟符号发生器和 用于找到最佳变换索引n0的最小PAPR评估单元。 接收机的各种实施例可以包括用于检测嵌入在OFDM信号中的变换索引的变换索引检测单元。
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公开(公告)号：US08982924B2
公开(公告)日：2015-03-17
申请号：US12660615
申请日：2010-03-02
Applicant: Rajendra Kumar
Inventor： Rajendra Kumar
Abstract: Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of −1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.
Abstract translation: 各种实施例涉及用于组合多个代码的系统和方法。 多个代码可以是具有可能的逻辑值为-1和+1的二进制代码，并且可以包括偶数个代码。 组合v0，k的输出可以由下式给出：v0 = sgn（vi），其中vi是第一时间的第一个多个代码的和。 呈现了各种代码中分配不同功率电平的实施例。
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公开(公告)号：US08711919B2
公开(公告)日：2014-04-29
申请号：US13434498
申请日：2012-03-29
Applicant: Rajendra Kumar
Inventor： Rajendra Kumar
IPC: H03H7/30
CPC classification number: H04L25/03885 , H04B1/1081 , H04L25/0204 , H04L25/0307 , H04L25/03292 , H04L27/3416 , H04L27/3845
Abstract: Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.
Abstract translation: 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。
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公开(公告)号：US08638890B2
公开(公告)日：2014-01-28
申请号：US13465606
申请日：2012-05-07
Applicant: Rajendra Kumar
Inventor： Rajendra Kumar
IPC: H03D1/04
CPC classification number: H04L27/12 , H04L27/156
Abstract: A receiver may comprise a complex mixer for converting the modulated signal to a complex modulated signal comprising a first in-phase component and a first quadrature component. The receiver may further comprise a digital demodulator. The digital demodulator may comprise at least one processor circuit programmed for applying a phase differencer for generating an output function in terms of a phase difference of the complex modulated signal. Applying the phase differencer may comprise converting the first in-phase component to a function of a phase difference of the first in-phase component expressed in digital time, and converting the first quadrature component to a function of the phase difference of the first quadrature component expressed in digital time. The at least one processor circuit of the digital demodulator may also be programmed for applying a four quadrant inverse tangent to the output function to generate the information signal.
Abstract translation: 接收机可以包括用于将调制信号转换成包括第一同相分量和第一正交分量的复调制信号的复合混频器。 接收机还可以包括数字解调器。 数字解调器可以包括至少一个处理器电路，其被编程用于施加相位差分器，用于根据复调制信号的相位差产生输出函数。 应用相位差分器可以包括将第一同相分量转换为以数字时间表示的第一同相分量的相位差的函数，并将第一正交分量转换为第一正交分量的相位差的函数 以数字时代表达。 数字解调器的至少一个处理器电路也可以被编程为向输出功能施加四象限反正切以产生信息信号。
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公开(公告)号：US08612651B2
公开(公告)日：2013-12-17
申请号：US12599062
申请日：2008-05-14
Applicant: Johannes Boonstra , Sundaravaradan Rangarajan , Rajendra Kumar
Inventor： Johannes Boonstra , Sundaravaradan Rangarajan , Rajendra Kumar
CPC classification number: G06F5/12
Abstract: A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.
Abstract translation: FIFO存储器电路用于在具有不同时钟域的电路之间进行接口。 电路具有FIFO存储器（10），由第一时钟域的时钟定时并且控制写入数据的存储器位置的写指针电路（16）以及由第二时钟的时钟脉冲定时的读指针电路 并控制读取数据的存储器位置。 读写指针电路采用灰度编码。 存储电路还包括一个重写写指针电路（30），它具有与写指针电路（16）同步增加的写指针地址，并且具有选择的开始写地址，使得重写写指针地址落在写指针之后 地址电路由与FIFO存储器（10）的大小对应的多个地址位置。 比较器（34）将读取指针电路地址与用于确定FIFO存储器的完整状态的重复写指针电路地址进行比较。
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