公开(公告)号：US20130214428A1

公开(公告)日：2013-08-22

申请号：US13772089

申请日：2013-02-20

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76892 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/1116 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer.

Abstract translation: 提供了一种半导体器件，其中易于将插头导电层和位于插头导电层上方的布线层彼此可靠地连接起来，并且可以抑制布线的下落。 插头导电层接触形成在半导体衬底的主表面上的源极/漏极区域。 接触导电层形成为与插头导电层的上表面和侧表面接触。 接触层形成在接触导电层上，以便电耦合到接触导电层。

公开(公告)号：US20150076612A1

公开(公告)日：2015-03-19

申请号：US14462376

申请日：2014-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI

IPC: H01L27/11 ,  H01L23/538

CPC classification number: H01L27/1104 ,  G11C5/025 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10891

Abstract: The semiconductor device includes a bit line, a word line intersecting the bit line, a plurality of first contact patterns, and a plurality of second contact patterns. The word line extends so as to intersect the bit line in plan view. Each of the first contact patterns is elongated in the direction in which the bit line extends in plan view. Each of the second contact patterns is elongated in directions inclined with respect to the respective directions in which the bit line and the word line extend in plan view. The first contact patterns and the second contact patterns are formed in the same layer over the main surface of a semiconductor substrate.

Abstract translation: 半导体器件包括位线，与位线相交的字线，多个第一接触图案和多个第二接触图案。 字线延伸，以便在平面图中与位线相交。 每个第一接触图案在平面图中位线延伸的方向上是细长的。 每个第二接触图案在相对于位线和字线在平面图中延伸的各个方向倾斜的方向上是细长的。 第一接触图案和第二接触图案形成在半导体衬底的主表面上的同一层中。

公开(公告)号：US20190259767A1

公开(公告)日：2019-08-22

申请号：US16399035

申请日：2019-04-30

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI

IPC: H01L27/11

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.

公开(公告)号：US20150076611A1

公开(公告)日：2015-03-19

申请号：US14462335

申请日：2014-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI

IPC: H01L27/11 ,  H01L29/51

CPC classification number: H01L27/1108 ,  H01L27/1112

Abstract: Provided are a semiconductor device in which the occurrence of a short circuit between a gate electrode and either of the source/drain regions of a transistor can be suppressed and a manufacturing method thereof. In the semiconductor device, a first insulating layer formed over the gate electrode and containing a silicon nitride has an upper surface having a depressed portion which is formed in a region over a second electrode layer of the gate electrode containing a silicide.

Abstract translation: 提供一种半导体器件，其中可以抑制栅电极和晶体管的源/漏区中的任一个之间的短路的发生及其制造方法。 在半导体器件中，形成在栅极上并含有氮化硅的第一绝缘层具有形成在包含硅化物的栅电极的第二电极层上的区域中的凹陷部的上表面。

公开(公告)号：US20180040365A1

公开(公告)日：2018-02-08

申请号：US15631101

申请日：2017-06-23

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI ,  Yoshiyuki ISHIGAKI ,  Toshiaki TAI ,  Hideaki YAMAKOSHI ,  Toshihiko HIROSE ,  Takuya ISHIDA

IPC: G11C11/417 ,  H01L23/535 ,  H01L21/265 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/4125 ,  H01L21/265 ,  H01L23/535 ,  H01L27/1104

Abstract: A semiconductor device which suppresses soft errors and functions as a non-volatile memory and a method for manufacturing the same. In the semiconductor device, a first non-volatile memory element and a second non-volatile memory element are electrically coupled to a first memory node and a second memory node through a first MOS transistor and a second MOS transistor respectively. A first capacitor and a second capacitor each have a storage node electrically coupled to the first memory node and the second memory node respectively and each have a cell plate to form a capacitance between the storage node and the cell plate.

公开(公告)号：US20160276270A1

公开(公告)日：2016-09-22

申请号：US15016360

申请日：2016-02-05

Applicant: Renesas Electronics Corporation

Inventor： Toshifumi IWASAKI ,  Yukio MAKI

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L23/5256 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/11

Abstract: An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.

Abstract translation: 本发明的目的是提供一种具有较少破裂或剥离的半导体器件及其制造方法。 半导体器件的熔丝部分具有电耦合到SRAM存储单元的位线。 位线被层间绝缘膜覆盖。 作为层间绝缘膜，形成硼掺杂BPTEOS膜。 位线上面有一个保险丝。 保险丝和位线通过接触插头彼此电耦合。 覆盖其位线的层间绝缘膜与接触插塞分离。

公开(公告)号：US20150076619A1

公开(公告)日：2015-03-19

申请号：US14459478

申请日：2014-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kenji ADACHI ,  Yukio MAKI

IPC: H01L27/11 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/1108 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Variations in the contact area between contact plugs are suppressed to suppress fluctuations in contact resistance. In three third interlayer insulating films, a contact hole is self-alignedly formed to extend through the portions thereof interposed between two wiring portions and the portions thereof interposed between two gate wiring portions and reach a first polysilicon plug. In the contact hole, a second polysilicon plug is formed to come in contact with the first polysilicon plug.

Abstract translation: 抑制接触插塞之间的接触面积的变化以抑制接触电阻的波动。 在三层第三层间绝缘膜中，接触孔被自对准地形成，以延伸穿过两个布线部分之间的部分和插入在两个栅极布线部分之间的部分并到达第一多晶硅插塞。 在接触孔中，形成第二多晶硅插塞以与第一多晶硅插塞接触。

公开(公告)号：US20140203441A1

公开(公告)日：2014-07-24

申请号：US14156026

申请日：2014-01-15

Applicant: Renesas Electronics Corporation

Inventor： Yukio MAKI

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/498 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5223 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed.The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line.

Abstract translation: 可以在夹在一对位线之间的区域中形成具有足够开口直径的开口，从而提供形成使用该开口的高质量接触的半导体器件。 半导体器件包括第一导电层，第一层间绝缘膜，位线，第一绝缘膜，第二层间绝缘膜和第二导电层。 覆盖位线的侧面的第一绝缘膜具有在比第一绝缘膜的最下部低的位置的区域中垂直于半导体基板的主表面的部分，沿着沿着 第一绝缘膜的半导体衬底的主表面覆盖位线的最下部的位线的侧表面。