公开(公告)号：US10895683B1

公开(公告)日：2021-01-19

申请号：US16601254

申请日：2019-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro Kuwajima ,  Yasutaka Nakashiba

IPC: G02B6/12 ,  G02B6/13

Abstract: A semiconductor device includes an insulating layer, an optical waveguide formed on the insulating layer, a multilayer wiring layer formed on the insulating layer such that the multilayer wiring layer covers the optical waveguide, and a first inductor formed in the multilayer wiring layer.

公开(公告)号：US11307479B2

公开(公告)日：2022-04-19

申请号：US16829509

申请日：2020-03-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro Kuwajima ,  Yasutaka Nakashiba

IPC: G02F1/025 ,  G02F1/225 ,  G02F1/01 ,  G02F1/21

Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.

公开(公告)号：US09209123B2

公开(公告)日：2015-12-08

申请号：US14508776

申请日：2014-10-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro Kuwajima

IPC: H01L23/48 ,  H01L21/4763 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.

Abstract translation: 同时实现布线槽的嵌入性的提高和布线与耦合构件之间的耦合故障的产生的抑制。 在垂直于穿过接触件的方向和第二布线延伸的方向的横截面中，接触的中心比第二布线的中心更靠近第二布线的第一侧表面。 此外，当第二布线的第一侧面与第二布线延伸的方向上的接触重叠的区域被设定为重叠区域时，至少重叠区域的下部的倾斜比 第二布线的侧表面的其它部分。

公开(公告)号：US10026689B2

公开(公告)日：2018-07-17

申请号：US15186734

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro Kuwajima ,  Akira Matsumoto ,  Yasutaka Nakashiba ,  Takashi Iwadare

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/495

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

公开(公告)号：US09553042B2

公开(公告)日：2017-01-24

申请号：US14832397

申请日：2015-08-21

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro Kuwajima

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5223 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first interlayer insulating film, a barrier insulating film formed over the first interlayer insulating film to cover the wiring and the electrode, a second interlayer insulating film formed over the barrier insulating film, and a second wiring and a second electrode for the capacitive element embedded in the second interlayer insulating film. The lower surface of the second wiring is positioned in the middle of the thickness of the second interlayer layer film, and the lower surface of the second electrode is in contact with the barrier insulating film. The barrier insulating film of a portion interposed between both electrodes functions as a capacitance insulating film of the capacitive element and is thicker than the barrier insulating film of a portion covering the first wiring.

Abstract translation: 其布线结构包括第一层间绝缘膜，第一布线和嵌入在第一层间绝缘膜中的电容元件的第一电极，形成在第一层间绝缘膜上以覆盖布线和电极的阻挡绝缘膜， 形成在所述阻挡绝缘膜上的第二层间绝缘膜，以及用于所述第二层间绝缘膜中的所述电容性元件的第二布线和第二电极。 第二布线的下表面位于第二层间膜的厚度的中间，第二电极的下表面与阻挡绝缘膜接触。 插入在两个电极之间的部分的阻挡绝缘膜用作电容性元件的电容绝缘膜，并且比覆盖第一布线的部分的阻挡绝缘膜厚。

公开(公告)号：US10886213B2

公开(公告)日：2021-01-05

申请号：US16984710

申请日：2020-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro Kuwajima ,  Yasutaka Nakashiba ,  Akira Matsumoto ,  Akio Ono ,  Tetsuya Iida

IPC: H03L7/06 ,  H01L23/522 ,  H01L49/02 ,  H03L7/099 ,  H01L29/93 ,  H01L27/06

Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.

公开(公告)号：US10211352B2

公开(公告)日：2019-02-19

申请号：US15797230

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Watanuki ,  Futoshi Komatsu ,  Tomoo Nakayama ,  Takashi Ogura ,  Teruhiro Kuwajima

IPC: H01L31/028 ,  H01L31/02 ,  H01L31/0232

Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.

公开(公告)号：US11145597B2

公开(公告)日：2021-10-12

申请号：US16505228

申请日：2019-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba ,  Teruhiro Kuwajima

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/768 ,  H01L27/092 ,  H01L27/06

Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.

公开(公告)号：US10818813B2

公开(公告)日：2020-10-27

申请号：US16188985

申请日：2018-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoo Nakayama ,  Shinichi Watanuki ,  Futoshi Komatsu ,  Teruhiro Kuwajima ,  Takashi Ogura ,  Hiroyuki Okuaki ,  Shigeaki Shimizu

IPC: H01L31/105 ,  H01L31/18 ,  G02B6/136 ,  G02B6/122 ,  H01L31/0224 ,  G02B6/12

Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.

公开(公告)号：US10553734B2

公开(公告)日：2020-02-04

申请号：US15980661

申请日：2018-05-15

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro Kuwajima ,  Shinichi Watanuki ,  Futoshi Komatsu ,  Tomoo Nakayama

IPC: H01L31/02 ,  H01L31/028 ,  H01L31/18 ,  H01L23/48 ,  H01L23/522 ,  H01L31/024 ,  H01L31/0232 ,  H01L31/0352 ,  H01L27/12 ,  G02B6/122 ,  G02F1/025 ,  G02B6/43

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film. A wire formed over a second interlayer insulating film is electrically coupled with the heater and the first and second contact portions via plugs embedded in the second interlayer insulating film.