公开(公告)号：US20130343113A1

公开(公告)日：2013-12-26

申请号：US13913363

申请日：2013-06-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryoji MATSUDA ,  Motoi ASHIDA ,  Yasumitsu MURAI

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C5/025 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228

Abstract: A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.

Abstract translation: 在不增加芯片面积的情况下降低噪声的半导体器件。 该器件用作MRAM，其中在硅衬底表面上形成存储器衬垫，并且存储器衬垫的中心区域用作存储器阵列，并且存储器阵列周围的区域用作虚拟存储器阵列。 在虚拟存储器阵列中，在每个位线，每个数字线和电源电压线之间形成电容器和接地电压线。 因此，在每个位线，数字线和电源电压线中流动的电流的峰值减小。

公开(公告)号：US20160056149A1

公开(公告)日：2016-02-25

申请号：US14809118

申请日：2015-07-24

Applicant: Renesas Electronics Corporation

Inventor： Yasuki YOSHIHISA ,  Ryoji MATSUDA

IPC: H01L27/02 ,  H01L29/06 ,  H01L49/02 ,  H01L29/861

CPC classification number: H01L27/0288 ,  H01L27/0255 ,  H01L29/36 ,  H01L29/8611

Abstract: A P-type epitaxial growth layer is formed on a P-type semiconductor substrate with an N-type buried region and a P-type buried region interposed therebetween. A cathode region, an anode region, and an N-type sinker region are formed in P-type epitaxial growth layer. A resistance element is formed on a surface of an isolation region that electrically isolates anode region and N-type sinker region. Resistance element has: one end portion electrically connected to each of anode region and N-type sinker region; and the other end portion electrically connected to a ground potential.

Abstract translation: 在P型半导体衬底上形成P型外延生长层，其中N型掩埋区和P型埋入区之间插入。 在P型外延生长层中形成阴极区域，阳极区域和N型沉降弧区域。 在隔离区域的电绝缘阳极区域和N型沉降片区域的表面上形成电阻元件。 电阻元件具有：电连接到阳极区域和N型沉降片区域中的每一个的一个端部; 并且另一端部电连接到地电位。