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公开(公告)号：US09621151B2
公开(公告)日：2017-04-11
申请号：US15157040
申请日：2016-05-17
发明人： Ryo Kanda , Koichi Yamazaki , Hiroshi Kuroiwa , Masatoshi Maeda , Tetsu Toda
IPC分类号： H03K3/00 , H03K17/082 , H03K3/356 , H03K5/01 , H03K5/24 , H03K17/567 , H01L23/528 , H01L23/00
CPC分类号： H03K17/0822 , H01L23/528 , H01L24/48 , H01L24/49 , H01L27/0922 , H01L29/0619 , H01L29/0642 , H01L29/0692 , H01L29/404 , H01L29/7823 , H01L29/7835 , H01L2224/0603 , H01L2224/48139 , H01L2224/48247 , H01L2224/4903 , H01L2924/00014 , H03K3/356 , H03K3/356113 , H03K5/01 , H03K5/04 , H03K5/24 , H03K5/2472 , H03K5/2481 , H03K17/567 , H03K2217/0081 , H01L2224/45099 , H01L2224/05599
摘要： A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been deteLutined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
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公开(公告)号：US20170019093A1
公开(公告)日：2017-01-19
申请号：US15157040
申请日：2016-05-17
发明人： Ryo KANDA , Koichi Yamazaki , Hiroshi Kuroiwa , Masatoshi Maeda , Tetsu Toda
IPC分类号： H03K17/082 , H03K17/567 , H03K5/24 , H03K3/356 , H03K5/01
CPC分类号： H03K17/0822 , H01L23/528 , H01L24/48 , H01L24/49 , H01L27/0922 , H01L29/0619 , H01L29/0642 , H01L29/0692 , H01L29/404 , H01L29/7823 , H01L29/7835 , H01L2224/0603 , H01L2224/48139 , H01L2224/48247 , H01L2224/4903 , H01L2924/00014 , H03K3/356 , H03K3/356113 , H03K5/01 , H03K5/04 , H03K5/24 , H03K5/2472 , H03K5/2481 , H03K17/567 , H03K2217/0081 , H01L2224/45099 , H01L2224/05599
摘要： A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
摘要翻译： 驱动器IC包括环形终止区域，以及分别布置在布局上的终止区域的内部和内部的第一区域和第二区域。 布置在浮动端子和第一感测节点之间并以电源电压驱动的感测MOS形成在终端区域中。 一种故障检测电路，当第一感测节点的电压高于在低侧驱动器将低侧晶体管驱动为导通状态的时间段中预先确定的判定电压时，检测故障的存在 形成在第一区域。
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公开(公告)号：US10224921B2
公开(公告)日：2019-03-05
申请号：US15444876
申请日：2017-02-28
发明人： Ryo Kanda , Koichi Yamazaki , Hiroshi Kuroiwa , Masatoshi Maeda , Tetsu Toda
IPC分类号： H03K17/082 , H03K17/567 , H03K5/01 , H03K5/24 , H03K3/356 , H03K5/04 , H01L27/092 , H01L29/06 , H01L29/40 , H01L29/78 , H01L23/528 , H01L23/00
摘要： A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
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公开(公告)号：US09831816B2
公开(公告)日：2017-11-28
申请号：US15232176
申请日：2016-08-09
发明人： Toshiya Nozawa , Yoshitaro Kondo , Yusuke Sugawara , Shoichi Kamimura , Masatoshi Maeda , Yasuhiro Shirai
CPC分类号： H02P29/68 , H02M7/48 , H02P29/027
摘要： Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
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