公开(公告)号：US10658855B2

公开(公告)日：2020-05-19

申请号：US15827169

申请日：2017-11-30

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Shigeru Maeta ,  Toshio Kimura ,  Atsushi Mitamura ,  Akira Negishi ,  Gary S. Jacobson

IPC: H02J7/02 ,  H02J7/00

Abstract: A transformer less battery charger system. In one embodiment, the battery charger system includes input terminals for receiving an AC voltage, output terminals for receiving terminals of a rechargeable battery pack, and a non-isolated DC-DC converter coupled between the input terminals and the output terminals. A device is also coupled somewhere between the input terminals and the output terminals. The device is configured to selectively and indirectly couple the input terminals to the output terminals. More particularly, the device indirectly couples the input terminals to the output terminals when the rechargeable battery pack terminals are received by the output terminals, and the device indirectly decouples the input terminals from the output terminals when the rechargeable battery pack terminals are separated from the output terminals.

公开(公告)号：US10594149B2

公开(公告)日：2020-03-17

申请号：US15606577

申请日：2017-05-26

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Tsutomu Kawano ,  Koji Kashimoto ,  Takao Hidaka ,  Tsuyoshi Ota ,  Ryoji Kato

IPC: H02J7/00 ,  H01M10/48 ,  G01R19/00 ,  G01R31/382

Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.

公开(公告)号：US10069415B2

公开(公告)日：2018-09-04

申请号：US15206990

申请日：2016-07-11

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Tomoaki Uno ,  Hirokazu Kato ,  Nobuyoshi Matsuura

IPC: H01L29/76 ,  H02M3/158 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L27/06 ,  H01L49/02 ,  H01L29/423 ,  H01L29/49 ,  H02M1/08 ,  H03K7/08 ,  H02M1/44 ,  H03K17/16 ,  H03K17/687

Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.

公开(公告)号：US20180062501A1

公开(公告)日：2018-03-01

申请号：US15804241

申请日：2017-11-06

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Ryotaro Kudo ,  Hideo Ishii ,  Kenichi Nakano

IPC: H02M1/088 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M1/088 ,  H02M3/158 ,  H02M2001/0054 ,  Y02B70/1491

Abstract: A step down convertor with a distributed driving system. In one embodiment, an apparatus is disclosed that includes an inductor coupled to an output node. The apparatus also includes first and second circuits. The first circuit can transmit current to the output node via the inductor, and the second can transmit current to the output node via the inductor. The apparatus also includes a third circuit for modifying operational aspects of the first circuit or the second circuit based on a magnitude of current flowing through the inductor.

公开(公告)号：US20180047756A1

公开(公告)日：2018-02-15

申请号：US15235878

申请日：2016-08-12

Applicant: Renesas Electronics America Inc.

Inventor： Kenji Yoshida ,  Tetsuo Sato ,  Shigeru Maeta ,  Toshio Kimura

IPC: H01L27/12 ,  H03K17/687 ,  H03K7/08 ,  H03K17/691 ,  H01L29/786 ,  H01L23/538

CPC classification number: H01L27/0688 ,  H01L23/528 ,  H01L23/5386 ,  H01L25/0657 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/7869 ,  H03K7/08

Abstract: A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.

公开(公告)号：US09866126B2

公开(公告)日：2018-01-09

申请号：US14922269

申请日：2015-10-26

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato

IPC: H02M3/335

CPC classification number: H02M3/33546 ,  H02M3/33523

Abstract: A method and apparatus for isolating voltages while transmitting data signals. In one embodiment of the method, a modulation circuit modulates a carrier signal using an input data signal. A demodulation circuit receives the modulated carrier signal via a first capacitor coupled in series between the modulation circuit and the demodulation circuit. The demodulation circuit also receives the carrier signal via a second capacitor coupled in series between the demodulation circuit and the circuit that generates the carrier signal. The demodulation circuit demodulates the modulated carrier signal using the carrier signal.

公开(公告)号：US20170207642A1

公开(公告)日：2017-07-20

申请号：US15406288

申请日：2017-01-13

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Shigeru Maeta ,  Toshio Kimura ,  Kenji Yoshida

IPC: H02J7/00 ,  H01L29/786

CPC classification number: H02J7/0031 ,  H01L27/1225 ,  H01L27/124 ,  H02J7/0029 ,  H02J7/0068 ,  H02J7/0072 ,  H02J2007/0037

Abstract: An apparatus and method for use in devices such as rechargeable battery packs. The apparatus, in one embodiment, includes an integrated circuit comprising a first circuit, a second circuit, and a thin film transistor (TFT). The first circuit is configured to generate a square wave signal. The second circuit is configured to convert the square wave signal to a direct current (DC) signal. The TFT is configured to activate and conduct current in response to the DC control signal.

公开(公告)号：US20150070940A1

公开(公告)日：2015-03-12

申请号：US14299186

申请日：2014-06-09

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Kazuhito Ayukawa ,  Hiroshi Murakami

IPC: H02M3/335

CPC classification number: H02M3/1584 ,  H02M2003/1586

Abstract: A multi-phase transformer type DC-DC converter. In one embodiment, the multi-phase transformer type DC-DC converter includes a plurality of DC-DC converters comprising a plurality of transformers, respectively, wherein the plurality of DC-DC converters are coupled in parallel between an input and an output. A circuit is coupled to the plurality of DC-DC converters and configured to generate a plurality of clock signals for use by the plurality of DC-DC converters, respectively, wherein the plurality of clock signals are phase shifted with respect to each other.

Abstract translation: 多相变压器型DC-DC转换器。 在一个实施例中，多相变压器型DC-DC转换器包括分别包括多个变压器的多个DC-DC转换器，其中多个DC-DC转换器在输入和输出之间并联耦合。 电路耦合到多个DC-DC转换器，并且被配置为分别产生多个时钟信号供多个DC-DC转换器使用，其中多个时钟信号相对于彼此相移。

公开(公告)号：US10985673B1

公开(公告)日：2021-04-20

申请号：US16749841

申请日：2020-01-22

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato

IPC: H02M7/5395 ,  H03C1/54 ,  H02M1/08 ,  H02M1/38 ,  H02M3/335

Abstract: One or more embodiments relate to a circuit that can be used to prevent cross conduction in an SMPS including multiple half-bridge modules connected in parallel to a single output inductor and driven by a single pulse width modulation (PWM) signal. According to certain aspects, each high-side driver and low-side driver in a single half-bridge module is synchronized in their switching with corresponding high-side drivers and low-side drivers in other half-bridge modules.

公开(公告)号：US10050620B2

公开(公告)日：2018-08-14

申请号：US14634195

申请日：2015-02-27

Applicant: Renesas Electronics America Inc.

Inventor： Tetsuo Sato ,  Koichi Yamazaki

IPC: H02M3/155 ,  H03K17/687 ,  H03K17/567 ,  H03K17/74 ,  H03K17/0416 ,  H02M7/00

Abstract: An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.