公开(公告)号：US20240170571A1

公开(公告)日：2024-05-23

申请号：US18516760

申请日：2023-11-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori HOSHINO ,  Hiroya SHIMOYAMA ,  Toshimune KANBARA ,  Masataka NOMURA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407

Abstract: A semiconductor device includes a vertical MOSFET in which a trench including a gate electrode and a field plate electrode therebelow at a gate potential and a trench including a gate electrode and a field plate electrode therebelow at a source potential are alternately arranged on an upper surface of a semiconductor substrate in a plan view.

公开(公告)号：US20180019160A1

公开(公告)日：2018-01-18

申请号：US15592241

申请日：2017-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi KACHI ,  Yoshinori HOSHINO ,  Senichirou NAGASE

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L29/15 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent the breakage of an element and in which the control of impurity amounts is less susceptible to variations in manufacturing processes. A semiconductor substrate has a front surface and includes hole portions extending from the front surface to an inside of the substrate. N-type regions are formed in the semiconductor substrate. At wall surfaces of the hole portions, p-type regions are formed to configure p-n junction with the n-type regions. Each of the p-type regions includes a low-concentration region and a high-concentration region formed at the wall surface of each hole portion. A width of the high-concentration region along the wall surface of the hole portion becomes smaller from the front surface toward a deeper position.

公开(公告)号：US20180358434A1

公开(公告)日：2018-12-13

申请号：US15950977

申请日：2018-04-11

Applicant: Renesas Electronics Corporation

Inventor： Senichirou NAGASE ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/872

Abstract: A deep trench which reaches a predetermined depth from one principal surface is formed in an element region of a semiconductor substrate. A TEOS oxide film and a polycrystalline silicon film are formed so as to fill the deep trench. In formation of a MOSFET and in formation of a protective insulating film on/over a surface of an element region by thermal oxidation, a silicon thermal oxide film grows, the TEOS oxide film contracts and the polycrystalline silicon film expands when oxidized and turning into a silicon oxide film, and thereby an embedded insulator is formed in the deep trench.

公开(公告)号：US20140235020A1

公开(公告)日：2014-08-21

申请号：US14261497

申请日：2014-04-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke ARAI ,  Yoshito NAKAZAWA ,  Ikuo HARA ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO ,  Tsuyoshi TABATA

IPC: H01L29/66

CPC classification number: H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract translation: 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。

公开(公告)号：US20170229572A1

公开(公告)日：2017-08-10

申请号：US15428350

申请日：2017-02-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Senichirou NAGASE ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66734 ,  H01L29/7813

Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.

公开(公告)号：US20200321464A1

公开(公告)日：2020-10-08

申请号：US16827150

申请日：2020-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Senichirou NAGASE ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66

Abstract: In a deep trench DTC reaching a predetermined depth from a first main surface of a semiconductor substrate SUB, a plurality of columnar conductors CCB including plugs PUG and field plates FP are formed. A p type impurity layer PIL is formed along the side wall surface of the deep trench DTC. Between the bottom of the plug PUG and the bottom of the p type impurity layer PIL, the field plate FP and the p type impurity layer PIL are positioned to face each other via an insulating film FIF interposed therebetween. Between the bottom of the p type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned to face each other via the insulating film FIF interposed therebetween.