公开(公告)号：US20180138325A1

公开(公告)日：2018-05-17

申请号：US15797230

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Futoshi KOMATSU ,  Tomoo NAKAYAMA ,  Takashi OGURA ,  Teruhiro KUWAJIMA

IPC: H01L31/028 ,  H01L31/0232 ,  H01L31/02

CPC classification number: H01L31/028 ,  H01L31/02005 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/105

Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.

公开(公告)号：US20190198703A1

公开(公告)日：2019-06-27

申请号：US16188985

申请日：2018-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoo NAKAYAMA ,  Shinichi WATANUKI ,  Futoshi KOMATSU ,  Teruhiro KUWAJIMA ,  Takashi OGURA ,  Hiroyuki OKUAKI ,  Shigeaki SHIMIZU

IPC: H01L31/105 ,  H01L31/18 ,  G02B6/122 ,  G02B6/136

Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.

公开(公告)号：US20180366321A1

公开(公告)日：2018-12-20

申请号：US15934710

申请日：2018-03-23

Applicant: Renesas Electronics Corporation

Inventor： Tomoo NAKAYAMA ,  Tatsuya USAMI

IPC: H01L21/02 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/02164 ,  H01L21/02274 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/32139 ,  H01L21/823814 ,  H01L29/66477

Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.

公开(公告)号：US20180083154A1

公开(公告)日：2018-03-22

申请号：US15703525

申请日：2017-09-13

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro KUWAJIMA ,  Shinichi WATANUKI ,  Futoshi KOMATSU ,  Tomoo NAKAYAMA

IPC: H01L31/105 ,  H01L31/028 ,  H01L31/18 ,  H01L31/0224

CPC classification number: H01L31/105 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547 ,  Y02P70/521

Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.

公开(公告)号：US20210184054A1

公开(公告)日：2021-06-17

申请号：US16951692

申请日：2020-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Masami SAWADA ,  Tatsuya USAMI ,  Tomoo NAKAYAMA

IPC: H01L29/861 ,  H01L29/24 ,  H01L29/66

Abstract: A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity.

公开(公告)号：US20210165160A1

公开(公告)日：2021-06-03

申请号：US16700580

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Seigo NAMIOKA ,  Tomoo NAKAYAMA

IPC: G02B6/122 ,  G02B6/13

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.

公开(公告)号：US20180090636A1

公开(公告)日：2018-03-29

申请号：US15656212

申请日：2017-07-21

Applicant: Renesas Electronics Corporation

Inventor： Tomoo NAKAYAMA

IPC: H01L31/105 ,  H01L31/028 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L31/1055 ,  G02B6/12002 ,  G02B6/43 ,  G02B2006/12061 ,  H01L31/02005 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/035272 ,  H01L31/1804

Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.

公开(公告)号：US20230387219A1

公开(公告)日：2023-11-30

申请号：US18185079

申请日：2023-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Futoshi KOMATSU ,  Tomoo NAKAYAMA ,  Katsuhiro UCHIMURA ,  Hiroshi INAGAWA

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/56 ,  H01L21/288

CPC classification number: H01L29/401 ,  H01L29/66348 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02359 ,  H01L21/304 ,  H01L21/56 ,  H01L21/288 ,  H01L29/4236

Abstract: A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.

公开(公告)号：US20190006535A1

公开(公告)日：2019-01-03

申请号：US15980661

申请日：2018-05-15

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro KUWAJIMA ,  Shinichi WATANUKI ,  Futoshi KOMATSU ,  Tomoo NAKAYAMA

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/024 ,  H01L31/02 ,  H01L31/028 ,  G02B6/43 ,  G02F1/025

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film. A wire formed over a second interlayer insulating film is electrically coupled with the heater and the first and second contact portions via plugs embedded in the second interlayer insulating film.

公开(公告)号：US20170170306A1

公开(公告)日：2017-06-15

申请号：US15361303

申请日：2016-11-25

Applicant: Renesas Electronics Corporation

Inventor： Tomoo NAKAYAMA ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7788 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.