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公开(公告)号：US11516421B2
公开(公告)日：2022-11-29
申请号：US16737527
申请日：2020-01-08
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Osamu Matsumoto , Masanori Otsuka , Fukashi Morishita
Abstract: A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.
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公开(公告)号：US10257457B2
公开(公告)日：2019-04-09
申请号：US15797085
申请日：2017-10-30
Applicant: Renesas Electronics Corporation
Inventor： Osamu Matsumoto , Fukashi Morishita
Abstract: Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.
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3.发明授权公开(公告)号：US09620214B2
公开(公告)日：2017-04-11
申请号：US14691125
申请日：2015-04-20
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
CPC classification number: G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
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公开(公告)号：US12040813B2
公开(公告)日：2024-07-16
申请号：US17886033
申请日：2022-08-11
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yoichi Iizuka , Fukashi Morishita
CPC classification number: H03M1/368 , H03K23/44 , H03K23/542 , H03M1/0872 , H03M1/50
Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.
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公开(公告)号：US11968465B2
公开(公告)日：2024-04-23
申请号：US17841183
申请日：2022-06-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Norihito Katou , Fukashi Morishita
IPC: H04N25/75 , H03M1/56 , H04N25/616 , H04N25/77
Abstract: A technique capable of improving linearity at a low illuminance is provided. A solid-state sensing image device includes: a pixel array including a plurality pixels arranged in a matrix form and a plurality of pixel signal lines connected to the plurality of pixels and receiving pixel signals supplied from the plurality pixels; a column-parallel A/D converting circuit connected to the plurality of pixel signal lines; and a reference-voltage generating circuit generating ramp-wave reference voltage that linearly changes in accordance with time passage. The column-parallel A/D converting circuit includes a first A/D converter, the first A/D converter includes: a first input terminal connected to the pixel signal line; a second input terminal receiving the reference voltage; and an offset generating circuit connected to the first input terminal and generating an offset voltage for the first input terminal.
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Patent Agency Ranking
公开(公告)号：US11800254B2
公开(公告)日：2023-10-24
申请号：US17850264
申请日：2022-06-27
Applicant: Renesas Electronics Corporation
Inventor： Fukashi Morishita
Abstract: An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.
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公开(公告)号：US10321086B2
公开(公告)日：2019-06-11
申请号：US15704997
申请日：2017-09-14
Applicant: Renesas Electronics Corporation
Inventor： Kazuhiro Ueda , Fukashi Morishita
IPC: H04N5/378 , H04N5/3745 , H04N5/347
Abstract: A semiconductor device includes a pixel array including a plurality of pixels arranged in a matrix, each pixel including a first switch and a second switch, a scanning circuit, in a first mode, enabling a first signal to be output from the pixel by setting the first and second switches to “off” in a period before a first timing, enabling a second signal to be output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and enabling a third signal to be output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing, and a first AD (Analog/Digital) converter, in a second mode, capable of performing AD conversion by comparing the difference between the second signal and the first signal with a reference signal.
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公开(公告)号：US09590652B2
公开(公告)日：2017-03-07
申请号：US14702492
申请日：2015-05-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shunsuke Okura , Fukashi Morishita
CPC classification number: H03M1/468 , H03M1/38 , H03M1/46 , H03M1/804 , H04N5/374 , H04N5/37455 , H04N5/378
Abstract: The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n−1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/D conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n−1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.
Abstract translation: 本发明提供一种小型便宜的固态成像装置。 包括在固态成像装置的连续比较型A / D转换器中的AD / A转换器包括多路复用器，其选择参考电压VR0至VR16中的任何一个，并且当执行粗略A / D转换时将其设置为模拟参考信号， 并且当执行精细的A / D转换时，其选择参考电压VR0至VR16的参考电压VR（n-1）至VR（n + 2），以及基于参考电压产生模拟参考信号的电容器阵列 当进行精细的A / D转换时，VR（n-1）至VR（n + 2）。 因此，可以在不使用冗余电容器的情况下降低参考电压的稳定误差。
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公开(公告)号：US09300892B2
公开(公告)日：2016-03-29
申请号：US14256680
申请日：2014-04-18
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US09042148B2
公开(公告)日：2015-05-26
申请号：US14151606
申请日：2014-01-09
Applicant: Renesas Electronics Corporation
Inventor： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
CPC classification number: G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。
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