公开(公告)号：US20170352651A1

公开(公告)日：2017-12-07

申请号：US15171987

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Albert KUMAR ,  Hai DANG ,  Sreeker DUNDIGAL ,  Vasisht VADI

IPC: H01L27/02 ,  H01L29/786 ,  H01L29/10 ,  H01L29/94 ,  H01L27/06

CPC classification number: H01L27/0251 ,  H01L27/0207 ,  H01L27/0288 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/092 ,  H01L29/1095 ,  H01L29/7869 ,  H01L29/94

Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.

公开(公告)号：US20150084161A1

公开(公告)日：2015-03-26

申请号：US14038663

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Eugene Robert WORLEY ,  Reza JALILIZEINALI ,  Sreeker DUNDIGAL

IPC: H01L23/60 ,  H01L27/06

CPC classification number: H01L23/60 ,  H01L27/0285 ,  H01L27/0682 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

Abstract: A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.

Abstract translation: 系统互连包括具有第一RC时间常数的第一电阻器 - 电容（RC）钳位。 系统互连还包括具有第二RC时间常数的第二RC钳位。 第一和第二RC夹具沿着系统互连排列。 另外，第一RC时间常数与第二RC时间常数不同。

公开(公告)号：US20230411956A1

公开(公告)日：2023-12-21

申请号：US18364164

申请日：2023-08-02

Applicant: QUALCOMM Incorporated

Inventor： Sreeker DUNDIGAL ,  Reza JALILIZEINALI ,  Krishna Chaitanya CHILLARA ,  Wen-Yi CHEN

IPC: H02H9/04 ,  H01L27/02 ,  H03K17/082

CPC classification number: H02H9/046 ,  H02H1/0007 ,  H03K17/0822 ,  H01L27/0292

Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.

公开(公告)号：US20230008489A1

公开(公告)日：2023-01-12

申请号：US17370894

申请日：2021-07-08

Applicant: QUALCOMM Incorporated

Inventor： Wen-Yi CHEN ,  Reza JALILIZEINALI ,  Sreeker DUNDIGAL ,  Krishna Chaitanya CHILLARA ,  Gregory LYNCH

IPC: H02H9/04 ,  H01L27/02

Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

公开(公告)号：US20250158390A1

公开(公告)日：2025-05-15

申请号：US18508052

申请日：2023-11-13

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo CHEN ,  Chiew-Guan TAN ,  Sreeker DUNDIGAL

IPC: H02H9/04 ,  H02H1/00

Abstract: An apparatus including: an overvoltage detector configured to generate an overvoltage indicating signal indicating whether a first voltage at an input/output (I/O) port is above an overvoltage threshold; a control circuit configured to generate a control signal based on the overvoltage indicating signal; a pseudo power source coupled to the I/O port and configured to provide a supply voltage for the control circuit; and a clamp circuit configured to generate a shunt current from the I/O port through an electrostatic discharge (ESD) protection diode, wherein the shunt current is enabled or disabled based on the control signal.

公开(公告)号：US20210408786A1

公开(公告)日：2021-12-30

申请号：US17355016

申请日：2021-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sreeker DUNDIGAL ,  Reza JALILIZEINALI ,  Krishna Chaitanya CHILLARA ,  Wen-Yi CHEN

IPC: H02H9/04 ,  H01L27/02 ,  H03K17/082

Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.

公开(公告)号：US20210407990A1

公开(公告)日：2021-12-30

申请号：US17354659

申请日：2021-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sreeker DUNDIGAL ,  Reza JALILIZEINALI ,  Krishna Chaitanya CHILLARA ,  Wen-Yi CHEN

IPC: H01L27/02 ,  G06F30/3953 ,  G06F30/367 ,  H03H7/38

Abstract: A chip includes a pad and a driver having an output coupled to the pad. The chip also includes one or more diodes coupled between the pad and a ground bus, wherein the one or more diodes are in a forward direction from the pad to the ground bus.

公开(公告)号：US20170288398A1

公开(公告)日：2017-10-05

申请号：US15088035

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Eugene Robert WORLEY ,  Reza JALILIZEINALI ,  Sreeker DUNDIGAL ,  Wen-Yi CHEN ,  Krishna Chaitanya CHILLARA ,  Taeghyun KANG

IPC: H02H9/04 ,  H03K19/0185 ,  H03M9/00

CPC classification number: H02H9/046 ,  H03K19/00315 ,  H03K19/018528 ,  H03K19/018592 ,  H03M9/00

Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.