公开(公告)号：US20180287835A1

公开(公告)日：2018-10-04

申请号：US15920270

申请日：2018-03-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Helena Deirdre O'SHEA ,  Chiew-Guan TAN ,  ZhenQi CHEN ,  Wilson Jianbo CHEN ,  Richard Dominic WIETFELDT

IPC: H04L27/00 ,  H03K3/011 ,  H03K5/01 ,  H04B3/46 ,  H04B3/06 ,  H04L25/02 ,  H04L25/03 ,  H04L29/06

Abstract: Systems, methods, and apparatus for managing digital communication interfaces coupled to data communication links are disclosed. In one example, the digital communication interfaces provide methods, protocols and techniques that may be used to provide a common slew rate for signals transmitted on a communication link that may be operated at multiple different voltage ranges. A method may include determining a first voltage range defined for transmitting signals over the communication link when the over the communication link is operated in a first mode of operation, configuring a line driver to operate within the first voltage range with a common slew rate that applies to each of a plurality of modes of operation, and transmitting first data over the communication link in one or more signals that switch within the first voltage range with the common slew rate. Each mode of operation may define a different voltage range for transmitting signals.

公开(公告)号：US20250158390A1

公开(公告)日：2025-05-15

申请号：US18508052

申请日：2023-11-13

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo CHEN ,  Chiew-Guan TAN ,  Sreeker DUNDIGAL

IPC: H02H9/04 ,  H02H1/00

Abstract: An apparatus including: an overvoltage detector configured to generate an overvoltage indicating signal indicating whether a first voltage at an input/output (I/O) port is above an overvoltage threshold; a control circuit configured to generate a control signal based on the overvoltage indicating signal; a pseudo power source coupled to the I/O port and configured to provide a supply voltage for the control circuit; and a clamp circuit configured to generate a shunt current from the I/O port through an electrostatic discharge (ESD) protection diode, wherein the shunt current is enabled or disabled based on the control signal.

公开(公告)号：US20230145180A1

公开(公告)日：2023-05-11

申请号：US17521651

申请日：2021-11-08

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo CHEN ,  Aliasgar PRESSWALA ,  Chiew-Guan (Kelvin) TAN

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.

公开(公告)号：US20210111720A1

公开(公告)日：2021-04-15

申请号：US17008068

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Sumit RAO ,  Wilson Jianbo CHEN ,  Chiew-Guan TAN

IPC: H03K19/0185 ,  H03K19/0175 ,  H03K19/003

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.