Abstract:
Systems and methods for decoding bitstreams are described. The bitstreams may be encoded using a punctured convolution code and received from a wireless network. A puncture pattern associated with a modulation and coding scheme used to encode the bitstream is determined, and punctured log-likelihood ratios (LLRs) generated from the bitstream are ignored while decoding the bitstream. The puncture pattern may be characterized by one or more algorithms that identify punctured LLRs in a repetitive sequence of LLRs. A decoder may exclude punctured LLRs from calculations related to bitstream decoding. The decoder may comprise a Viterbi decoder or an algebraic decoder. Other aspects, embodiments, and features are also claimed and described.
Abstract:
Aspects of the present disclosure provides a wireless communication apparatus configured to handle adjacent-channel interference (ACI) and spur. The apparatus receives a signal utilizing a communication interface. The apparatus is configured to perform a single discrete Fourier transform (DFT) on the signal to generate frequency domain data. The apparatus is further configured to determine respective energy of a plurality of adjacent channels of the signal utilizing the frequency domain data. The apparatus is further configured to determine one or more potential interfering channels among the adjacent channels, wherein each of the potential interfering channels has an energy greater than a qualifying threshold. The apparatus is further configured to identify one or more dominant interfering channels from among the potential interfering channels. The apparatus is further configured to detect ACI based on the one or more dominant interfering channels.
Abstract:
An apparatus includes memory storing an instruction that identifies a first register, a second register, and a third register. Upon execution of the instruction by a processor, a vector addition operation is performed by the processor to add first values from the first register to second values from the second register. A vector subtraction operation is also performed upon execution of the instruction to subtract the second value from third values from the third register. A vector compare operation is also performed upon execution of the instruction to compare results of the vector addition operation to results of the vector subtraction operation.
Abstract:
Aspects of the present disclosure provides a wireless communication apparatus configured to handle adjacent-channel interference (ACI) and spur. The apparatus receives a signal utilizing a communication interface. The apparatus is configured to perform a single discrete Fourier transform (DFT) on the signal to generate frequency domain data. The apparatus is further configured to determine respective energy of a plurality of adjacent channels of the signal utilizing the frequency domain data. The apparatus is further configured to determine one or more potential interfering channels among the adjacent channels, wherein each of the potential interfering channels has an energy greater than a qualifying threshold. The apparatus is further configured to identify one or more dominant interfering channels from among the potential interfering channels. The apparatus is further configured to detect ACI based on the one or more dominant interfering channels.
Abstract:
A method for wireless communications is described. The method includes beginning a voice call using a voice services over adaptive multi-user channels on one slot receiver. Pilot signal knowledge is obtained. Interferers knowledge is also obtained. Error metrics are computed using the pilot signal knowledge and the interferers knowledge. The method further includes selecting between the voice services over adaptive multi-user channels on one slot receiver and a legacy receiver for the voice call based on the error metrics. Other aspects, embodiments and features are also claimed and described.
Abstract:
An apparatus includes memory storing an instruction that identifies a first register, a second register, and a third register. Upon execution of the instruction by a processor, a vector addition operation is performed by the processor to add first values from the first register to second values from the second register. A vector subtraction operation is also performed upon execution of the instruction to subtract the second value from third values from the third register. A vector compare operation is also performed upon execution of the instruction to compare results of the vector addition operation to results of the vector subtraction operation.